clk: rockchip: fix the incorrect pclk_edp div width for RK3399

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.
Reported-by: NLin Huang <hl@rock-chips.com>
Signed-off-by: NXing Zheng <zhengxing@rock-chips.com>
Tested-by: NLin Huang <hl@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

drivers/clk/rockchip/clk-rk3399.c

@@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(11), 8, GFLAGS),
 
 	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
-			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
+			RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
 			RK3399_CLKGATE_CON(11), 11, GFLAGS),
 	GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(32), 12, GFLAGS),