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kernel_linux
提交 3395f6e9 编写于 作者: T Tomas Winkler 提交者： John W. Linville
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iwlwifi: rename iwl-4965-io.h to iwl-io.h 

This patch renames iwl-4965-io.h back to iw-io.h
it also remove 4965 from all functions it supplies
Signed-off-by: NTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: NReinette Chatre <reinette.chatre@intel.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 ab53d8af
展开全部 隐藏空白更改
内联 并排
Showing with 364 addition and 366 deletion
drivers/net/wireless/iwlwifi/iwl-4965.c
浏览文件 @ 3395f6e9
...@@ -41,6 +41,7 @@ ...@@ -41,6 +41,7 @@
#include "iwl-eeprom.h" #include "iwl-eeprom.h"
#include "iwl-core.h" #include "iwl-core.h"
#include "iwl-4965.h" #include "iwl-4965.h"
#include "iwl-io.h"
#include "iwl-helpers.h" #include "iwl-helpers.h"
/* module parameters */ /* module parameters */
...@@ -315,20 +316,20 @@ int iwl4965_hw_rxq_stop(struct iwl_priv *priv) ...@@ -315,20 +316,20 @@ int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc) { if (rc) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return rc; return rc;
} }
/* stop Rx DMA */ /* stop Rx DMA */
iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
(1 << 24), 1000); (1 << 24), 1000);
if (rc < 0) if (rc < 0)
IWL_ERROR("Can't stop Rx DMA.\n"); IWL_ERROR("Can't stop Rx DMA.\n");
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return 0; return 0;
...@@ -372,7 +373,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) ...@@ -372,7 +373,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
ret = iwl4965_grab_nic_access(priv); ret = iwl_grab_nic_access(priv);
if (ret) { if (ret) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return ret; return ret;
...@@ -385,15 +386,15 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) ...@@ -385,15 +386,15 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
&val); &val);
if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VAUX, APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
~APMG_PS_CTRL_MSK_PWR_SRC); ~APMG_PS_CTRL_MSK_PWR_SRC);
} else } else
iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
~APMG_PS_CTRL_MSK_PWR_SRC); ~APMG_PS_CTRL_MSK_PWR_SRC);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return ret; return ret;
...@@ -406,7 +407,7 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) ...@@ -406,7 +407,7 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
unsigned int rb_size; unsigned int rb_size;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc) { if (rc) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return rc; return rc;
...@@ -418,34 +419,34 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq) ...@@ -418,34 +419,34 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
/* Stop Rx DMA */ /* Stop Rx DMA */
iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
/* Reset driver's Rx queue write index */ /* Reset driver's Rx queue write index */
iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
/* Tell device where to find RBD circular buffer in DRAM */ /* Tell device where to find RBD circular buffer in DRAM */
iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
rxq->dma_addr >> 8); rxq->dma_addr >> 8);
/* Tell device where in DRAM to update its Rx status */ /* Tell device where in DRAM to update its Rx status */
iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
(priv->hw_setting.shared_phys + (priv->hw_setting.shared_phys +
offsetof(struct iwl4965_shared, val0)) >> 4); offsetof(struct iwl4965_shared, val0)) >> 4);
/* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */ /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
rb_size | rb_size |
/*0x10 << 4 | */ /*0x10 << 4 | */
(RX_QUEUE_SIZE_LOG << (RX_QUEUE_SIZE_LOG <<
FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT)); FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
/* /*
* iwl4965_write32(priv,CSR_INT_COAL_REG,0); * iwl_write32(priv,CSR_INT_COAL_REG,0);
*/ */
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return 0; return 0;
...@@ -458,13 +459,13 @@ static int iwl4965_kw_init(struct iwl_priv *priv) ...@@ -458,13 +459,13 @@ static int iwl4965_kw_init(struct iwl_priv *priv)
int rc; int rc;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc) if (rc)
goto out; goto out;
iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG, iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
priv->kw.dma_addr >> 4); priv->kw.dma_addr >> 4);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
out: out:
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return rc; return rc;
...@@ -524,7 +525,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv) ...@@ -524,7 +525,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (unlikely(rc)) { if (unlikely(rc)) {
IWL_ERROR("TX reset failed"); IWL_ERROR("TX reset failed");
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
...@@ -532,8 +533,8 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv) ...@@ -532,8 +533,8 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
} }
/* Turn off all Tx DMA channels */ /* Turn off all Tx DMA channels */
iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0); iwl_write_prph(priv, KDR_SCD_TXFACT, 0);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
/* Tell 4965 where to find the keep-warm buffer */ /* Tell 4965 where to find the keep-warm buffer */
...@@ -580,11 +581,11 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv) ...@@ -580,11 +581,11 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
/* nic_init */ /* nic_init */
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS, iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL, rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
if (rc < 0) { if (rc < 0) {
...@@ -593,26 +594,25 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv) ...@@ -593,26 +594,25 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
return rc; return rc;
} }
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc) { if (rc) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return rc; return rc;
} }
iwl4965_read_prph(priv, APMG_CLK_CTRL_REG); iwl_read_prph(priv, APMG_CLK_CTRL_REG);
iwl4965_write_prph(priv, APMG_CLK_CTRL_REG, iwl_write_prph(priv, APMG_CLK_CTRL_REG,
APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
APMG_CLK_VAL_BSM_CLK_RQT); iwl_read_prph(priv, APMG_CLK_CTRL_REG);
iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
udelay(20); udelay(20);
iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG, iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS); APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32); iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
/* Determine HW type */ /* Determine HW type */
...@@ -648,26 +648,24 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv) ...@@ -648,26 +648,24 @@ int iwl4965_hw_nic_init(struct iwl_priv *priv)
/* set CSR_HW_CONFIG_REG for uCode use */ /* set CSR_HW_CONFIG_REG for uCode use */
iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG, iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR49_HW_IF_CONFIG_REG_BIT_4965_R | CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI | CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI); CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc < 0) { if (rc < 0) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
IWL_DEBUG_INFO("Failed to init the card\n"); IWL_DEBUG_INFO("Failed to init the card\n");
return rc; return rc;
} }
iwl4965_read_prph(priv, APMG_PS_CTRL_REG); iwl_read_prph(priv, APMG_PS_CTRL_REG);
iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG, iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
APMG_PS_CTRL_VAL_RESET_REQ);
udelay(5); udelay(5);
iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG, iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
APMG_PS_CTRL_VAL_RESET_REQ);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
iwl4965_hw_card_show_info(priv); iwl4965_hw_card_show_info(priv);
...@@ -720,16 +718,16 @@ int iwl4965_hw_nic_stop_master(struct iwl_priv *priv) ...@@ -720,16 +718,16 @@ int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
/* set stop master bit */ /* set stop master bit */
iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
reg_val = iwl4965_read32(priv, CSR_GP_CNTRL); reg_val = iwl_read32(priv, CSR_GP_CNTRL);
if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
(reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
IWL_DEBUG_INFO("Card in power save, master is already " IWL_DEBUG_INFO("Card in power save, master is already "
"stopped\n"); "stopped\n");
else { else {
rc = iwl4965_poll_bit(priv, CSR_RESET, rc = iwl_poll_bit(priv, CSR_RESET,
CSR_RESET_REG_FLAG_MASTER_DISABLED, CSR_RESET_REG_FLAG_MASTER_DISABLED,
CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
if (rc < 0) { if (rc < 0) {
...@@ -756,18 +754,17 @@ void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv) ...@@ -756,18 +754,17 @@ void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
/* Stop each Tx DMA channel, and wait for it to be idle */ /* Stop each Tx DMA channel, and wait for it to be idle */
for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) { for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
if (iwl4965_grab_nic_access(priv)) { if (iwl_grab_nic_access(priv)) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
continue; continue;
} }
iwl4965_write_direct32(priv, iwl_write_direct32(priv,
IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
0x0); iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG, IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE (txq_id), 200);
(txq_id), 200); iwl_release_nic_access(priv);
iwl4965_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
} }
...@@ -784,29 +781,29 @@ int iwl4965_hw_nic_reset(struct iwl_priv *priv) ...@@ -784,29 +781,29 @@ int iwl4965_hw_nic_reset(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
udelay(10); udelay(10);
iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
rc = iwl4965_poll_bit(priv, CSR_RESET, rc = iwl_poll_bit(priv, CSR_RESET,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25); CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
udelay(10); udelay(10);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (!rc) { if (!rc) {
iwl4965_write_prph(priv, APMG_CLK_EN_REG, iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_DMA_CLK_RQT |
APMG_CLK_VAL_BSM_CLK_RQT); APMG_CLK_VAL_BSM_CLK_RQT);
udelay(10); udelay(10);
iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG, iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS); APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
} }
clear_bit(STATUS_HCMD_ACTIVE, &priv->status); clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
...@@ -872,7 +869,7 @@ void iwl4965_rf_kill_ct_config(struct iwl_priv *priv) ...@@ -872,7 +869,7 @@ void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
int ret = 0; int ret = 0;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
...@@ -1733,9 +1730,9 @@ static void iwl4965_bg_txpower_work(struct work_struct *work) ...@@ -1733,9 +1730,9 @@ static void iwl4965_bg_txpower_work(struct work_struct *work)
*/ */
static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index) static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
{ {
iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, iwl_write_direct32(priv, HBUS_TARG_WRPTR,
(index & 0xff) | (txq_id << 8)); (index & 0xff) | (txq_id << 8));
iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index); iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
} }
/** /**
...@@ -1755,7 +1752,7 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv, ...@@ -1755,7 +1752,7 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
/* Set up and activate */ /* Set up and activate */
iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id), iwl_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
(scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) | (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
...@@ -1807,46 +1804,46 @@ int iwl4965_alive_notify(struct iwl_priv *priv) ...@@ -1807,46 +1804,46 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
priv->chain_noise_data.delta_gain_code[i] = priv->chain_noise_data.delta_gain_code[i] =
CHAIN_NOISE_DELTA_GAIN_INIT_VAL; CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
#endif /* CONFIG_IWL4965_SENSITIVITY*/ #endif /* CONFIG_IWL4965_SENSITIVITY*/
ret = iwl4965_grab_nic_access(priv); ret = iwl_grab_nic_access(priv);
if (ret) { if (ret) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return ret; return ret;
} }
/* Clear 4965's internal Tx Scheduler data base */ /* Clear 4965's internal Tx Scheduler data base */
priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR); priv->scd_base_addr = iwl_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
iwl4965_write_targ_mem(priv, a, 0); iwl_write_targ_mem(priv, a, 0);
for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4) for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
iwl4965_write_targ_mem(priv, a, 0); iwl_write_targ_mem(priv, a, 0);
for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4) for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
iwl4965_write_targ_mem(priv, a, 0); iwl_write_targ_mem(priv, a, 0);
/* Tel 4965 where to find Tx byte count tables */ /* Tel 4965 where to find Tx byte count tables */
iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR, iwl_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
(priv->hw_setting.shared_phys + (priv->hw_setting.shared_phys +
offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10); offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
/* Disable chain mode for all queues */ /* Disable chain mode for all queues */
iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0); iwl_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
/* Initialize each Tx queue (including the command queue) */ /* Initialize each Tx queue (including the command queue) */
for (i = 0; i < priv->hw_setting.max_txq_num; i++) { for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
/* TFD circular buffer read/write indexes */ /* TFD circular buffer read/write indexes */
iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0); iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
/* Max Tx Window size for Scheduler-ACK mode */ /* Max Tx Window size for Scheduler-ACK mode */
iwl4965_write_targ_mem(priv, priv->scd_base_addr + iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i), SCD_CONTEXT_QUEUE_OFFSET(i),
(SCD_WIN_SIZE << (SCD_WIN_SIZE <<
SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
/* Frame limit */ /* Frame limit */
iwl4965_write_targ_mem(priv, priv->scd_base_addr + iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i) + SCD_CONTEXT_QUEUE_OFFSET(i) +
sizeof(u32), sizeof(u32),
(SCD_FRAME_LIMIT << (SCD_FRAME_LIMIT <<
...@@ -1854,11 +1851,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv) ...@@ -1854,11 +1851,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
} }
iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK, iwl_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
(1 << priv->hw_setting.max_txq_num) - 1); (1 << priv->hw_setting.max_txq_num) - 1);
/* Activate all Tx DMA/FIFO channels */ /* Activate all Tx DMA/FIFO channels */
iwl4965_write_prph(priv, KDR_SCD_TXFACT, iwl_write_prph(priv, KDR_SCD_TXFACT,
SCD_TXFACT_REG_TXFIFO_MASK(0, 7)); SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
...@@ -1870,7 +1867,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv) ...@@ -1870,7 +1867,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
} }
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return ret; return ret;
...@@ -2929,22 +2926,22 @@ int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq ...@@ -2929,22 +2926,22 @@ int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq
int txq_id = txq->q.id; int txq_id = txq->q.id;
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc) { if (rc) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return rc; return rc;
} }
/* Circular buffer (TFD queue in DRAM) physical base address */ /* Circular buffer (TFD queue in DRAM) physical base address */
iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
txq->q.dma_addr >> 8); txq->q.dma_addr >> 8);
/* Enable DMA channel, using same id as for TFD queue */ /* Enable DMA channel, using same id as for TFD queue */
iwl4965_write_direct32( iwl_write_direct32(
priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return 0; return 0;
...@@ -4259,7 +4256,7 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, ...@@ -4259,7 +4256,7 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
{ {
/* Simply stop the queue, but don't change any configuration; /* Simply stop the queue, but don't change any configuration;
* the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
iwl4965_write_prph(priv, iwl_write_prph(priv,
KDR_SCD_QUEUE_STATUS_BITS(txq_id), KDR_SCD_QUEUE_STATUS_BITS(txq_id),
(0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
(1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
...@@ -4280,24 +4277,24 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id, ...@@ -4280,24 +4277,24 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
return -EINVAL; return -EINVAL;
} }
ret = iwl4965_grab_nic_access(priv); ret = iwl_grab_nic_access(priv);
if (ret) if (ret)
return ret; return ret;
iwl4965_tx_queue_stop_scheduler(priv, txq_id); iwl4965_tx_queue_stop_scheduler(priv, txq_id);
iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id)); iwl_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
/* supposes that ssn_idx is valid (!= 0xFFF) */ /* supposes that ssn_idx is valid (!= 0xFFF) */
iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id)); iwl_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
iwl4965_txq_ctx_deactivate(priv, txq_id); iwl4965_txq_ctx_deactivate(priv, txq_id);
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
return 0; return 0;
} }
...@@ -4432,14 +4429,14 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, ...@@ -4432,14 +4429,14 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
tbl_dw_addr = priv->scd_base_addr + tbl_dw_addr = priv->scd_base_addr +
SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr); tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
if (txq_id & 0x1) if (txq_id & 0x1)
tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
else else
tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw); iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
return 0; return 0;
} }
...@@ -4469,7 +4466,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id, ...@@ -4469,7 +4466,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid); iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
spin_lock_irqsave(&priv->lock, flags); spin_lock_irqsave(&priv->lock, flags);
rc = iwl4965_grab_nic_access(priv); rc = iwl_grab_nic_access(priv);
if (rc) { if (rc) {
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return rc; return rc;
...@@ -4482,7 +4479,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id, ...@@ -4482,7 +4479,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id); iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
/* Set this queue as a chain-building queue */ /* Set this queue as a chain-building queue */
iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id)); iwl_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
/* Place first TFD at index corresponding to start sequence number. /* Place first TFD at index corresponding to start sequence number.
* Assumes that ssn_idx is valid (!= 0xFFF) */ * Assumes that ssn_idx is valid (!= 0xFFF) */
...@@ -4491,22 +4488,22 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id, ...@@ -4491,22 +4488,22 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
/* Set up Tx window size and frame limit for this queue */ /* Set up Tx window size and frame limit for this queue */
iwl4965_write_targ_mem(priv, iwl_write_targ_mem(priv,
priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id), priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
(SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
iwl4965_write_targ_mem(priv, priv->scd_base_addr + iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id)); iwl_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags); spin_unlock_irqrestore(&priv->lock, flags);
return 0; return 0;
......
drivers/net/wireless/iwlwifi/iwl-4965.h
浏览文件 @ 3395f6e9
...@@ -1266,6 +1266,5 @@ extern const struct iwl_channel_info *iwl_get_channel_info( ...@@ -1266,6 +1266,5 @@ extern const struct iwl_channel_info *iwl_get_channel_info(
const struct iwl_priv *priv, enum ieee80211_band band, u16 channel); const struct iwl_priv *priv, enum ieee80211_band band, u16 channel);
/* Requires full declaration of iwl_priv before including */ /* Requires full declaration of iwl_priv before including */
#include "iwl-4965-io.h"
#endif /* __iwl4965_4965_h__ */ #endif /* __iwl4965_4965_h__ */
drivers/net/wireless/iwlwifi/iwl-debugfs.c
浏览文件 @ 3395f6e9
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
#include "iwl-4965.h" #include "iwl-4965.h"
#include "iwl-debug.h" #include "iwl-debug.h"
#include "iwl-4965-io.h" #include "iwl-io.h"
/* create and remove of files */ /* create and remove of files */
...@@ -141,9 +141,9 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file, ...@@ -141,9 +141,9 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
printk(KERN_DEBUG "offset is: 0x%x\tlen is: 0x%x\n", printk(KERN_DEBUG "offset is: 0x%x\tlen is: 0x%x\n",
priv->dbgfs->sram_offset, priv->dbgfs->sram_len); priv->dbgfs->sram_offset, priv->dbgfs->sram_len);
iwl4965_grab_nic_access(priv); iwl_grab_nic_access(priv);
for (i = priv->dbgfs->sram_len; i > 0; i -= 4) { for (i = priv->dbgfs->sram_len; i > 0; i -= 4) {
val = iwl4965_read_targ_mem(priv, priv->dbgfs->sram_offset + \ val = iwl_read_targ_mem(priv, priv->dbgfs->sram_offset + \
priv->dbgfs->sram_len - i); priv->dbgfs->sram_len - i);
if (i < 4) { if (i < 4) {
switch (i) { switch (i) {
...@@ -161,7 +161,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file, ...@@ -161,7 +161,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
pos += sprintf(buf+pos, "0x%08x ", val); pos += sprintf(buf+pos, "0x%08x ", val);
} }
pos += sprintf(buf+pos, "\n"); pos += sprintf(buf+pos, "\n");
iwl4965_release_nic_access(priv); iwl_release_nic_access(priv);
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
return ret; return ret;
......
drivers/net/wireless/iwlwifi/iwl-eeprom.c
浏览文件 @ 3395f6e9
...@@ -73,7 +73,7 @@ ...@@ -73,7 +73,7 @@
#include "iwl-core.h" #include "iwl-core.h"
#include "iwl-debug.h" #include "iwl-debug.h"
#include "iwl-eeprom.h" #include "iwl-eeprom.h"
#include "iwl-4965-io.h" #include "iwl-io.h"
/************************** EEPROM BANDS **************************** /************************** EEPROM BANDS ****************************
* *
...@@ -144,7 +144,7 @@ static const u8 iwl_eeprom_band_7[] = { /* 5.2 FAT channel */ ...@@ -144,7 +144,7 @@ static const u8 iwl_eeprom_band_7[] = { /* 5.2 FAT channel */
int iwlcore_eeprom_verify_signature(struct iwl_priv *priv) int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
{ {
u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP); u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) { if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp); IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
return -ENOENT; return -ENOENT;
...@@ -166,14 +166,14 @@ int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv) ...@@ -166,14 +166,14 @@ int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv)
for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
/* Request semaphore */ /* Request semaphore */
iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG, iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
/* See if we got it */ /* See if we got it */
ret = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG, ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
EEPROM_SEM_TIMEOUT); EEPROM_SEM_TIMEOUT);
if (ret >= 0) { if (ret >= 0) {
IWL_DEBUG_IO("Acquired semaphore after %d tries.\n", IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
count+1); count+1);
...@@ -187,7 +187,7 @@ EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore); ...@@ -187,7 +187,7 @@ EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore);
void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv) void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv)
{ {
iwl4965_clear_bit(priv, CSR_HW_IF_CONFIG_REG, iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
} }
...@@ -204,7 +204,7 @@ EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore); ...@@ -204,7 +204,7 @@ EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
int iwl_eeprom_init(struct iwl_priv *priv) int iwl_eeprom_init(struct iwl_priv *priv)
{ {
u16 *e = (u16 *)&priv->eeprom; u16 *e = (u16 *)&priv->eeprom;
u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP); u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
u32 r; u32 r;
int sz = sizeof(priv->eeprom); int sz = sizeof(priv->eeprom);
int ret; int ret;
...@@ -231,12 +231,12 @@ int iwl_eeprom_init(struct iwl_priv *priv) ...@@ -231,12 +231,12 @@ int iwl_eeprom_init(struct iwl_priv *priv)
/* eeprom is an array of 16bit values */ /* eeprom is an array of 16bit values */
for (addr = 0; addr < sz; addr += sizeof(u16)) { for (addr = 0; addr < sz; addr += sizeof(u16)) {
_iwl4965_write32(priv, CSR_EEPROM_REG, addr << 1); _iwl_write32(priv, CSR_EEPROM_REG, addr << 1);
_iwl4965_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD); _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT; for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
i += IWL_EEPROM_ACCESS_DELAY) { i += IWL_EEPROM_ACCESS_DELAY) {
r = _iwl4965_read_direct32(priv, CSR_EEPROM_REG); r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
if (r & CSR_EEPROM_REG_READ_VALID_MSK) if (r & CSR_EEPROM_REG_READ_VALID_MSK)
break; break;
udelay(IWL_EEPROM_ACCESS_DELAY); udelay(IWL_EEPROM_ACCESS_DELAY);
......
drivers/net/wireless/iwlwifi/iwl-4965-io.h → drivers/net/wireless/iwlwifi/iwl-io.h
浏览文件 @ 3395f6e9
...@@ -26,8 +26,8 @@ ...@@ -26,8 +26,8 @@
* *
*****************************************************************************/ *****************************************************************************/
#ifndef __iwl4965_io_h__ #ifndef __iwl_io_h__
#define __iwl4965_io_h__ #define __iwl_io_h__
#include <linux/io.h> #include <linux/io.h>
...@@ -49,8 +49,8 @@ ...@@ -49,8 +49,8 @@
* *
* If you wish to call the function without any debug or state checking, * If you wish to call the function without any debug or state checking,
* you should use the single _ prefix version (as is used by dependent IO * you should use the single _ prefix version (as is used by dependent IO
* routines, for example _iwl4965_read_direct32 calls the non-check version of * routines, for example _iwl_read_direct32 calls the non-check version of
* _iwl4965_read32.) * _iwl_read32.)
* *
* These declarations are *extremely* useful in quickly isolating code deltas * These declarations are *extremely* useful in quickly isolating code deltas
* which result in misconfiguring of the hardware I/O. In combination with * which result in misconfiguring of the hardware I/O. In combination with
...@@ -59,39 +59,39 @@ ...@@ -59,39 +59,39 @@
* *
*/ */
#define _iwl4965_write32(priv, ofs, val) writel((val), (priv)->hw_base + (ofs)) #define _iwl_write32(priv, ofs, val) writel((val), (priv)->hw_base + (ofs))
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_write32(const char *f, u32 l, struct iwl_priv *priv, static inline void __iwl_write32(const char *f, u32 l, struct iwl_priv *priv,
u32 ofs, u32 val) u32 ofs, u32 val)
{ {
IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l); IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
_iwl4965_write32(priv, ofs, val); _iwl_write32(priv, ofs, val);
} }
#define iwl4965_write32(priv, ofs, val) \ #define iwl_write32(priv, ofs, val) \
__iwl4965_write32(__FILE__, __LINE__, priv, ofs, val) __iwl_write32(__FILE__, __LINE__, priv, ofs, val)
#else #else
#define iwl4965_write32(priv, ofs, val) _iwl4965_write32(priv, ofs, val) #define iwl_write32(priv, ofs, val) _iwl_write32(priv, ofs, val)
#endif #endif
#define _iwl4965_read32(priv, ofs) readl((priv)->hw_base + (ofs)) #define _iwl_read32(priv, ofs) readl((priv)->hw_base + (ofs))
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline u32 __iwl4965_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs) static inline u32 __iwl_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs)
{ {
IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l); IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l);
return _iwl4965_read32(priv, ofs); return _iwl_read32(priv, ofs);
} }
#define iwl4965_read32(priv, ofs) __iwl4965_read32(__FILE__, __LINE__, priv, ofs) #define iwl_read32(priv, ofs) __iwl_read32(__FILE__, __LINE__, priv, ofs)
#else #else
#define iwl4965_read32(p, o) _iwl4965_read32(p, o) #define iwl_read32(p, o) _iwl_read32(p, o)
#endif #endif
static inline int _iwl4965_poll_bit(struct iwl_priv *priv, u32 addr, static inline int _iwl_poll_bit(struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout) u32 bits, u32 mask, int timeout)
{ {
int i = 0; int i = 0;
do { do {
if ((_iwl4965_read32(priv, addr) & mask) == (bits & mask)) if ((_iwl_read32(priv, addr) & mask) == (bits & mask))
return i; return i;
mdelay(10); mdelay(10);
i += 10; i += 10;
...@@ -100,57 +100,57 @@ static inline int _iwl4965_poll_bit(struct iwl_priv *priv, u32 addr, ...@@ -100,57 +100,57 @@ static inline int _iwl4965_poll_bit(struct iwl_priv *priv, u32 addr,
return -ETIMEDOUT; return -ETIMEDOUT;
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl4965_poll_bit(const char *f, u32 l, static inline int __iwl_poll_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 addr, struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout) u32 bits, u32 mask, int timeout)
{ {
int ret = _iwl4965_poll_bit(priv, addr, bits, mask, timeout); int ret = _iwl_poll_bit(priv, addr, bits, mask, timeout);
IWL_DEBUG_IO("poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n", IWL_DEBUG_IO("poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n",
addr, bits, mask, addr, bits, mask,
unlikely(ret == -ETIMEDOUT)?"timeout":"", f, l); unlikely(ret == -ETIMEDOUT)?"timeout":"", f, l);
return ret; return ret;
} }
#define iwl4965_poll_bit(priv, addr, bits, mask, timeout) \ #define iwl_poll_bit(priv, addr, bits, mask, timeout) \
__iwl4965_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout) __iwl_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout)
#else #else
#define iwl4965_poll_bit(p, a, b, m, t) _iwl4965_poll_bit(p, a, b, m, t) #define iwl_poll_bit(p, a, b, m, t) _iwl_poll_bit(p, a, b, m, t)
#endif #endif
static inline void _iwl4965_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) static inline void _iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{ {
_iwl4965_write32(priv, reg, _iwl4965_read32(priv, reg) | mask); _iwl_write32(priv, reg, _iwl_read32(priv, reg) | mask);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_set_bit(const char *f, u32 l, static inline void __iwl_set_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 reg, u32 mask) struct iwl_priv *priv, u32 reg, u32 mask)
{ {
u32 val = _iwl4965_read32(priv, reg) | mask; u32 val = _iwl_read32(priv, reg) | mask;
IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val); IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
_iwl4965_write32(priv, reg, val); _iwl_write32(priv, reg, val);
} }
#define iwl4965_set_bit(p, r, m) __iwl4965_set_bit(__FILE__, __LINE__, p, r, m) #define iwl_set_bit(p, r, m) __iwl_set_bit(__FILE__, __LINE__, p, r, m)
#else #else
#define iwl4965_set_bit(p, r, m) _iwl4965_set_bit(p, r, m) #define iwl_set_bit(p, r, m) _iwl_set_bit(p, r, m)
#endif #endif
static inline void _iwl4965_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) static inline void _iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{ {
_iwl4965_write32(priv, reg, _iwl4965_read32(priv, reg) & ~mask); _iwl_write32(priv, reg, _iwl_read32(priv, reg) & ~mask);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_clear_bit(const char *f, u32 l, static inline void __iwl_clear_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 reg, u32 mask) struct iwl_priv *priv, u32 reg, u32 mask)
{ {
u32 val = _iwl4965_read32(priv, reg) & ~mask; u32 val = _iwl_read32(priv, reg) & ~mask;
IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val); IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
_iwl4965_write32(priv, reg, val); _iwl_write32(priv, reg, val);
} }
#define iwl4965_clear_bit(p, r, m) __iwl4965_clear_bit(__FILE__, __LINE__, p, r, m) #define iwl_clear_bit(p, r, m) __iwl_clear_bit(__FILE__, __LINE__, p, r, m)
#else #else
#define iwl4965_clear_bit(p, r, m) _iwl4965_clear_bit(p, r, m) #define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m)
#endif #endif
static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv) static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
{ {
int ret; int ret;
u32 gp_ctl; u32 gp_ctl;
...@@ -165,7 +165,7 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv) ...@@ -165,7 +165,7 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv)
"wakes up NIC\n"); "wakes up NIC\n");
/* 10 msec allows time for NIC to complete its data save */ /* 10 msec allows time for NIC to complete its data save */
gp_ctl = _iwl4965_read32(priv, CSR_GP_CNTRL); gp_ctl = _iwl_read32(priv, CSR_GP_CNTRL);
if (gp_ctl & CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) { if (gp_ctl & CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY) {
IWL_DEBUG_RF_KILL("Wait for complete power-down, " IWL_DEBUG_RF_KILL("Wait for complete power-down, "
"gpctl = 0x%08x\n", gp_ctl); "gpctl = 0x%08x\n", gp_ctl);
...@@ -176,8 +176,8 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv) ...@@ -176,8 +176,8 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv)
} }
/* this bit wakes up the NIC */ /* this bit wakes up the NIC */
_iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ret = _iwl4965_poll_bit(priv, CSR_GP_CNTRL, ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50); CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
...@@ -193,7 +193,7 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv) ...@@ -193,7 +193,7 @@ static inline int _iwl4965_grab_nic_access(struct iwl_priv *priv)
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl4965_grab_nic_access(const char *f, u32 l, static inline int __iwl_grab_nic_access(const char *f, u32 l,
struct iwl_priv *priv) struct iwl_priv *priv)
{ {
if (atomic_read(&priv->restrict_refcnt)) if (atomic_read(&priv->restrict_refcnt))
...@@ -201,98 +201,98 @@ static inline int __iwl4965_grab_nic_access(const char *f, u32 l, ...@@ -201,98 +201,98 @@ static inline int __iwl4965_grab_nic_access(const char *f, u32 l,
"line %d.\n", l); "line %d.\n", l);
IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l); IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l);
return _iwl4965_grab_nic_access(priv); return _iwl_grab_nic_access(priv);
} }
#define iwl4965_grab_nic_access(priv) \ #define iwl_grab_nic_access(priv) \
__iwl4965_grab_nic_access(__FILE__, __LINE__, priv) __iwl_grab_nic_access(__FILE__, __LINE__, priv)
#else #else
#define iwl4965_grab_nic_access(priv) \ #define iwl_grab_nic_access(priv) \
_iwl4965_grab_nic_access(priv) _iwl_grab_nic_access(priv)
#endif #endif
static inline void _iwl4965_release_nic_access(struct iwl_priv *priv) static inline void _iwl_release_nic_access(struct iwl_priv *priv)
{ {
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
if (atomic_dec_and_test(&priv->restrict_refcnt)) if (atomic_dec_and_test(&priv->restrict_refcnt))
#endif #endif
_iwl4965_clear_bit(priv, CSR_GP_CNTRL, _iwl_clear_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_release_nic_access(const char *f, u32 l, static inline void __iwl_release_nic_access(const char *f, u32 l,
struct iwl_priv *priv) struct iwl_priv *priv)
{ {
if (atomic_read(&priv->restrict_refcnt) <= 0) if (atomic_read(&priv->restrict_refcnt) <= 0)
IWL_ERROR("Release unheld nic access at line %d.\n", l); IWL_ERROR("Release unheld nic access at line %d.\n", l);
IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l); IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l);
_iwl4965_release_nic_access(priv); _iwl_release_nic_access(priv);
} }
#define iwl4965_release_nic_access(priv) \ #define iwl_release_nic_access(priv) \
__iwl4965_release_nic_access(__FILE__, __LINE__, priv) __iwl_release_nic_access(__FILE__, __LINE__, priv)
#else #else
#define iwl4965_release_nic_access(priv) \ #define iwl_release_nic_access(priv) \
_iwl4965_release_nic_access(priv) _iwl_release_nic_access(priv)
#endif #endif
static inline u32 _iwl4965_read_direct32(struct iwl_priv *priv, u32 reg) static inline u32 _iwl_read_direct32(struct iwl_priv *priv, u32 reg)
{ {
return _iwl4965_read32(priv, reg); return _iwl_read32(priv, reg);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline u32 __iwl4965_read_direct32(const char *f, u32 l, static inline u32 __iwl_read_direct32(const char *f, u32 l,
struct iwl_priv *priv, u32 reg) struct iwl_priv *priv, u32 reg)
{ {
u32 value = _iwl4965_read_direct32(priv, reg); u32 value = _iwl_read_direct32(priv, reg);
if (!atomic_read(&priv->restrict_refcnt)) if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from %s %d\n", f, l); IWL_ERROR("Nic access not held from %s %d\n", f, l);
IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value, IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
f, l); f, l);
return value; return value;
} }
#define iwl4965_read_direct32(priv, reg) \ #define iwl_read_direct32(priv, reg) \
__iwl4965_read_direct32(__FILE__, __LINE__, priv, reg) __iwl_read_direct32(__FILE__, __LINE__, priv, reg)
#else #else
#define iwl4965_read_direct32 _iwl4965_read_direct32 #define iwl_read_direct32 _iwl_read_direct32
#endif #endif
static inline void _iwl4965_write_direct32(struct iwl_priv *priv, static inline void _iwl_write_direct32(struct iwl_priv *priv,
u32 reg, u32 value) u32 reg, u32 value)
{ {
_iwl4965_write32(priv, reg, value); _iwl_write32(priv, reg, value);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static void __iwl4965_write_direct32(u32 line, static void __iwl_write_direct32(u32 line,
struct iwl_priv *priv, u32 reg, u32 value) struct iwl_priv *priv, u32 reg, u32 value)
{ {
if (!atomic_read(&priv->restrict_refcnt)) if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line); IWL_ERROR("Nic access not held from line %d\n", line);
_iwl4965_write_direct32(priv, reg, value); _iwl_write_direct32(priv, reg, value);
} }
#define iwl4965_write_direct32(priv, reg, value) \ #define iwl_write_direct32(priv, reg, value) \
__iwl4965_write_direct32(__LINE__, priv, reg, value) __iwl_write_direct32(__LINE__, priv, reg, value)
#else #else
#define iwl4965_write_direct32 _iwl4965_write_direct32 #define iwl_write_direct32 _iwl_write_direct32
#endif #endif
static inline void iwl4965_write_reg_buf(struct iwl_priv *priv, static inline void iwl_write_reg_buf(struct iwl_priv *priv,
u32 reg, u32 len, u32 *values) u32 reg, u32 len, u32 *values)
{ {
u32 count = sizeof(u32); u32 count = sizeof(u32);
if ((priv != NULL) && (values != NULL)) { if ((priv != NULL) && (values != NULL)) {
for (; 0 < len; len -= count, reg += count, values++) for (; 0 < len; len -= count, reg += count, values++)
_iwl4965_write_direct32(priv, reg, *values); _iwl_write_direct32(priv, reg, *values);
} }
} }
static inline int _iwl4965_poll_direct_bit(struct iwl_priv *priv, static inline int _iwl_poll_direct_bit(struct iwl_priv *priv,
u32 addr, u32 mask, int timeout) u32 addr, u32 mask, int timeout)
{ {
int i = 0; int i = 0;
do { do {
if ((_iwl4965_read_direct32(priv, addr) & mask) == mask) if ((_iwl_read_direct32(priv, addr) & mask) == mask)
return i; return i;
mdelay(10); mdelay(10);
i += 10; i += 10;
...@@ -302,11 +302,11 @@ static inline int _iwl4965_poll_direct_bit(struct iwl_priv *priv, ...@@ -302,11 +302,11 @@ static inline int _iwl4965_poll_direct_bit(struct iwl_priv *priv,
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline int __iwl4965_poll_direct_bit(const char *f, u32 l, static inline int __iwl_poll_direct_bit(const char *f, u32 l,
struct iwl_priv *priv, struct iwl_priv *priv,
u32 addr, u32 mask, int timeout) u32 addr, u32 mask, int timeout)
{ {
int ret = _iwl4965_poll_direct_bit(priv, addr, mask, timeout); int ret = _iwl_poll_direct_bit(priv, addr, mask, timeout);
if (unlikely(ret == -ETIMEDOUT)) if (unlikely(ret == -ETIMEDOUT))
IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - " IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - "
...@@ -316,111 +316,111 @@ static inline int __iwl4965_poll_direct_bit(const char *f, u32 l, ...@@ -316,111 +316,111 @@ static inline int __iwl4965_poll_direct_bit(const char *f, u32 l,
"- %s %d\n", addr, mask, ret, f, l); "- %s %d\n", addr, mask, ret, f, l);
return ret; return ret;
} }
#define iwl4965_poll_direct_bit(priv, addr, mask, timeout) \ #define iwl_poll_direct_bit(priv, addr, mask, timeout) \
__iwl4965_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout) __iwl_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout)
#else #else
#define iwl4965_poll_direct_bit _iwl4965_poll_direct_bit #define iwl_poll_direct_bit _iwl_poll_direct_bit
#endif #endif
static inline u32 _iwl4965_read_prph(struct iwl_priv *priv, u32 reg) static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
{ {
_iwl4965_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); _iwl_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
return _iwl4965_read_direct32(priv, HBUS_TARG_PRPH_RDAT); return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline u32 __iwl4965_read_prph(u32 line, struct iwl_priv *priv, u32 reg) static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
{ {
if (!atomic_read(&priv->restrict_refcnt)) if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line); IWL_ERROR("Nic access not held from line %d\n", line);
return _iwl4965_read_prph(priv, reg); return _iwl_read_prph(priv, reg);
} }
#define iwl4965_read_prph(priv, reg) \ #define iwl_read_prph(priv, reg) \
__iwl4965_read_prph(__LINE__, priv, reg) __iwl_read_prph(__LINE__, priv, reg)
#else #else
#define iwl4965_read_prph _iwl4965_read_prph #define iwl_read_prph _iwl_read_prph
#endif #endif
static inline void _iwl4965_write_prph(struct iwl_priv *priv, static inline void _iwl_write_prph(struct iwl_priv *priv,
u32 addr, u32 val) u32 addr, u32 val)
{ {
_iwl4965_write_direct32(priv, HBUS_TARG_PRPH_WADDR, _iwl_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
((addr & 0x0000FFFF) | (3 << 24))); ((addr & 0x0000FFFF) | (3 << 24)));
_iwl4965_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val); _iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
} }
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_write_prph(u32 line, struct iwl_priv *priv, static inline void __iwl_write_prph(u32 line, struct iwl_priv *priv,
u32 addr, u32 val) u32 addr, u32 val)
{ {
if (!atomic_read(&priv->restrict_refcnt)) if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access from line %d\n", line); IWL_ERROR("Nic access from line %d\n", line);
_iwl4965_write_prph(priv, addr, val); _iwl_write_prph(priv, addr, val);
} }
#define iwl4965_write_prph(priv, addr, val) \ #define iwl_write_prph(priv, addr, val) \
__iwl4965_write_prph(__LINE__, priv, addr, val); __iwl_write_prph(__LINE__, priv, addr, val);
#else #else
#define iwl4965_write_prph _iwl4965_write_prph #define iwl_write_prph _iwl_write_prph
#endif #endif
#define _iwl4965_set_bits_prph(priv, reg, mask) \ #define _iwl_set_bits_prph(priv, reg, mask) \
_iwl4965_write_prph(priv, reg, (_iwl4965_read_prph(priv, reg) | mask)) _iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask))
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_set_bits_prph(u32 line, struct iwl_priv *priv, static inline void __iwl_set_bits_prph(u32 line, struct iwl_priv *priv,
u32 reg, u32 mask) u32 reg, u32 mask)
{ {
if (!atomic_read(&priv->restrict_refcnt)) if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line); IWL_ERROR("Nic access not held from line %d\n", line);
_iwl4965_set_bits_prph(priv, reg, mask); _iwl_set_bits_prph(priv, reg, mask);
} }
#define iwl4965_set_bits_prph(priv, reg, mask) \ #define iwl_set_bits_prph(priv, reg, mask) \
__iwl4965_set_bits_prph(__LINE__, priv, reg, mask) __iwl_set_bits_prph(__LINE__, priv, reg, mask)
#else #else
#define iwl4965_set_bits_prph _iwl4965_set_bits_prph #define iwl_set_bits_prph _iwl_set_bits_prph
#endif #endif
#define _iwl4965_set_bits_mask_prph(priv, reg, bits, mask) \ #define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \
_iwl4965_write_prph(priv, reg, ((_iwl4965_read_prph(priv, reg) & mask) | bits)) _iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits))
#ifdef CONFIG_IWLWIFI_DEBUG #ifdef CONFIG_IWLWIFI_DEBUG
static inline void __iwl4965_set_bits_mask_prph(u32 line, static inline void __iwl_set_bits_mask_prph(u32 line,
struct iwl_priv *priv, u32 reg, u32 bits, u32 mask) struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
{ {
if (!atomic_read(&priv->restrict_refcnt)) if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line); IWL_ERROR("Nic access not held from line %d\n", line);
_iwl4965_set_bits_mask_prph(priv, reg, bits, mask); _iwl_set_bits_mask_prph(priv, reg, bits, mask);
} }
#define iwl4965_set_bits_mask_prph(priv, reg, bits, mask) \ #define iwl_set_bits_mask_prph(priv, reg, bits, mask) \
__iwl4965_set_bits_mask_prph(__LINE__, priv, reg, bits, mask) __iwl_set_bits_mask_prph(__LINE__, priv, reg, bits, mask)
#else #else
#define iwl4965_set_bits_mask_prph _iwl4965_set_bits_mask_prph #define iwl_set_bits_mask_prph _iwl_set_bits_mask_prph
#endif #endif
static inline void iwl4965_clear_bits_prph(struct iwl_priv static inline void iwl_clear_bits_prph(struct iwl_priv
*priv, u32 reg, u32 mask) *priv, u32 reg, u32 mask)
{ {
u32 val = _iwl4965_read_prph(priv, reg); u32 val = _iwl_read_prph(priv, reg);
_iwl4965_write_prph(priv, reg, (val & ~mask)); _iwl_write_prph(priv, reg, (val & ~mask));
} }
static inline u32 iwl4965_read_targ_mem(struct iwl_priv *priv, u32 addr) static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
{ {
iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr); iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
return iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT); return iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
} }
static inline void iwl4965_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
{ {
iwl4965_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr); iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
iwl4965_write_direct32(priv, HBUS_TARG_MEM_WDAT, val); iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
} }
static inline void iwl4965_write_targ_mem_buf(struct iwl_priv *priv, u32 addr, static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
u32 len, u32 *values) u32 len, u32 *values)
{ {
iwl4965_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr); iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
for (; 0 < len; len -= sizeof(u32), values++) for (; 0 < len; len -= sizeof(u32), values++)
iwl4965_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values); iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
} }
#endif #endif
drivers/net/wireless/iwlwifi/iwl-led.c
浏览文件 @ 3395f6e9
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#include <asm/unaligned.h> #include <asm/unaligned.h>
#include "iwl-4965.h" #include "iwl-4965.h"
#include "iwl-io.h"
#include "iwl-core.h" #include "iwl-core.h"
#include "iwl-helpers.h" #include "iwl-helpers.h"
...@@ -85,9 +86,9 @@ static int iwl_send_led_cmd(struct iwl_priv *priv, ...@@ -85,9 +86,9 @@ static int iwl_send_led_cmd(struct iwl_priv *priv,
}; };
u32 reg; u32 reg;
reg = iwl4965_read32(priv, CSR_LED_REG); reg = iwl_read32(priv, CSR_LED_REG);
if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) if (reg != (reg & CSR_LED_BSM_CTRL_MSK))
iwl4965_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); iwl_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK);
return iwl_send_cmd(priv, &cmd); return iwl_send_cmd(priv, &cmd);
} }
...@@ -126,7 +127,7 @@ static int iwl4965_led_pattern(struct iwl_priv *priv, int led_id, ...@@ -126,7 +127,7 @@ static int iwl4965_led_pattern(struct iwl_priv *priv, int led_id,
static int iwl4965_led_on_reg(struct iwl_priv *priv, int led_id) static int iwl4965_led_on_reg(struct iwl_priv *priv, int led_id)
{ {
IWL_DEBUG_LED("led on %d\n", led_id); IWL_DEBUG_LED("led on %d\n", led_id);
iwl4965_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_ON); iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_ON);
return 0; return 0;
} }
...@@ -150,7 +151,7 @@ int iwl4965_led_off(struct iwl_priv *priv, int led_id) ...@@ -150,7 +151,7 @@ int iwl4965_led_off(struct iwl_priv *priv, int led_id)
static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id) static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id)
{ {
IWL_DEBUG_LED("radio off\n"); IWL_DEBUG_LED("radio off\n");
iwl4965_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_OFF); iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_OFF);
return 0; return 0;
} }
......
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