drm/amdgpu: change ELM/BAF to Polaris10/Polaris11

Adjust to preferred code names.
Signed-off-by: NFlora Cui <Flora.Cui@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

@@ -681,8 +681,8 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
 		result = AMDGPU_UCODE_ID_CP_MEC1;
 		break;
 	case CGS_UCODE_ID_CP_MEC_JT2:
-		if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_BAFFIN
-		  || adev->asic_type == CHIP_ELLESMERE)
+		if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11
+		  || adev->asic_type == CHIP_POLARIS10)
 			result = AMDGPU_UCODE_ID_CP_MEC2;
 		else
 			result = AMDGPU_UCODE_ID_CP_MEC1;
@@ -742,17 +742,17 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 		case CHIP_FIJI:
 			strcpy(fw_name, "amdgpu/fiji_smc.bin");
 			break;
-		case CHIP_BAFFIN:
+		case CHIP_POLARIS11:
 			if (type == CGS_UCODE_ID_SMU)
-				strcpy(fw_name, "amdgpu/baffin_smc.bin");
+				strcpy(fw_name, "amdgpu/polaris11_smc.bin");
 			else if (type == CGS_UCODE_ID_SMU_SK)
-				strcpy(fw_name, "amdgpu/baffin_smc_sk.bin");
+				strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
 			break;
-		case CHIP_ELLESMERE:
+		case CHIP_POLARIS10:
 			if (type == CGS_UCODE_ID_SMU)
-				strcpy(fw_name, "amdgpu/ellesmere_smc.bin");
+				strcpy(fw_name, "amdgpu/polaris10_smc.bin");
 			else if (type == CGS_UCODE_ID_SMU_SK)
-				strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin");
+				strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
 			break;
 		default:
 			DRM_ERROR("SMC firmware not supported\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

@@ -59,8 +59,8 @@ static const char *amdgpu_asic_name[] = {
 	"FIJI",
 	"CARRIZO",
 	"STONEY",
-	"ELLESMERE",
-	"BAFFIN",
+	"POLARIS10",
+	"POLARIS11",
 	"LAST",
 };
 
@@ -1148,8 +1148,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
 	case CHIP_TOPAZ:
 	case CHIP_TONGA:
 	case CHIP_FIJI:
-	case CHIP_BAFFIN:
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS11:
+	case CHIP_POLARIS10:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
 		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

@@ -277,16 +277,16 @@ static const struct pci_device_id pciidlist[] = {
 	{0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
 	/* stoney */
 	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
-	/* Baffin */
-	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN},
-	/* Ellesmere */
-	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
-	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE},
+	/* Polaris11 */
+	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+	/* Polaris10 */
+	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 
 	{0, 0, 0}
 };

drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

@@ -99,10 +99,12 @@ static int amdgpu_pp_early_init(void *handle)
 
 #ifdef CONFIG_DRM_AMD_POWERPLAY
 	switch (adev->asic_type) {
+	case CHIP_POLARIS11:
+	case CHIP_POLARIS10:
+		adev->pp_enabled = true;
+		break;
 	case CHIP_TONGA:
 	case CHIP_FIJI:
-	case CHIP_BAFFIN:
-	case CHIP_ELLESMERE:
 		adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
 		break;
 	case CHIP_CARRIZO:

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

@@ -54,8 +54,8 @@
 #define FIRMWARE_CARRIZO	"amdgpu/carrizo_uvd.bin"
 #define FIRMWARE_FIJI		"amdgpu/fiji_uvd.bin"
 #define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
-#define FIRMWARE_ELLESMERE	"amdgpu/ellesmere_uvd.bin"
-#define FIRMWARE_BAFFIN         "amdgpu/baffin_uvd.bin"
+#define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
+#define FIRMWARE_POLARIS11         "amdgpu/polaris11_uvd.bin"
 
 /**
  * amdgpu_uvd_cs_ctx - Command submission parser context
@@ -87,8 +87,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA);
 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 MODULE_FIRMWARE(FIRMWARE_FIJI);
 MODULE_FIRMWARE(FIRMWARE_STONEY);
-MODULE_FIRMWARE(FIRMWARE_ELLESMERE);
-MODULE_FIRMWARE(FIRMWARE_BAFFIN);
+MODULE_FIRMWARE(FIRMWARE_POLARIS10);
+MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 
 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
@@ -135,11 +135,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 	case CHIP_STONEY:
 		fw_name = FIRMWARE_STONEY;
 		break;
-	case CHIP_ELLESMERE:
-		fw_name = FIRMWARE_ELLESMERE;
+	case CHIP_POLARIS10:
+		fw_name = FIRMWARE_POLARIS10;
 		break;
-	case CHIP_BAFFIN:
-		fw_name = FIRMWARE_BAFFIN;
+	case CHIP_POLARIS11:
+		fw_name = FIRMWARE_POLARIS11;
 		break;
 	default:
 		return -EINVAL;

drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

@@ -50,8 +50,8 @@
 #define FIRMWARE_CARRIZO	"amdgpu/carrizo_vce.bin"
 #define FIRMWARE_FIJI		"amdgpu/fiji_vce.bin"
 #define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"
-#define FIRMWARE_ELLESMERE	"amdgpu/ellesmere_vce.bin"
-#define FIRMWARE_BAFFIN         "amdgpu/baffin_vce.bin"
+#define FIRMWARE_POLARIS10	"amdgpu/polaris10_vce.bin"
+#define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
 
 #ifdef CONFIG_DRM_AMDGPU_CIK
 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
@@ -64,8 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA);
 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 MODULE_FIRMWARE(FIRMWARE_FIJI);
 MODULE_FIRMWARE(FIRMWARE_STONEY);
-MODULE_FIRMWARE(FIRMWARE_ELLESMERE);
-MODULE_FIRMWARE(FIRMWARE_BAFFIN);
+MODULE_FIRMWARE(FIRMWARE_POLARIS10);
+MODULE_FIRMWARE(FIRMWARE_POLARIS11);
 
 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
 
@@ -117,11 +117,11 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
 	case CHIP_STONEY:
 		fw_name = FIRMWARE_STONEY;
 		break;
-	case CHIP_ELLESMERE:
-		fw_name = FIRMWARE_ELLESMERE;
+	case CHIP_POLARIS10:
+		fw_name = FIRMWARE_POLARIS10;
 		break;
-	case CHIP_BAFFIN:
-		fw_name = FIRMWARE_BAFFIN;
+	case CHIP_POLARIS11:
+		fw_name = FIRMWARE_POLARIS11;
 		break;
 
 	default:

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

@@ -132,7 +132,7 @@ static const u32 stoney_golden_settings_a11[] =
 	mmFBC_MISC, 0x1f311fff, 0x14302000,
 };
 
-static const u32 baffin_golden_settings_a11[] =
+static const u32 polaris11_golden_settings_a11[] =
 {
 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
@@ -141,7 +141,7 @@ static const u32 baffin_golden_settings_a11[] =
 	mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 };
 
-static const u32 ellesmere_golden_settings_a11[] =
+static const u32 polaris10_golden_settings_a11[] =
 {
 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
@@ -165,15 +165,15 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 						 stoney_golden_settings_a11,
 						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		amdgpu_program_register_sequence(adev,
-						 baffin_golden_settings_a11,
-						 (const u32)ARRAY_SIZE(baffin_golden_settings_a11));
+						 polaris11_golden_settings_a11,
+						 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		amdgpu_program_register_sequence(adev,
-						 ellesmere_golden_settings_a11,
-						 (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11));
+						 polaris10_golden_settings_a11,
+						 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
 		break;
 	default:
 		break;
@@ -1611,10 +1611,10 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
 	case CHIP_STONEY:
 		adev->mode_info.audio.num_pins = 7;
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		adev->mode_info.audio.num_pins = 8;
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		adev->mode_info.audio.num_pins = 6;
 		break;
 	default:
@@ -2411,8 +2411,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
 	u32 pll_in_use;
 	int pll;
 
-	if ((adev->asic_type == CHIP_ELLESMERE) ||
-	    (adev->asic_type == CHIP_BAFFIN)) {
+	if ((adev->asic_type == CHIP_POLARIS10) ||
+	    (adev->asic_type == CHIP_POLARIS11)) {
 		struct amdgpu_encoder *amdgpu_encoder =
 			to_amdgpu_encoder(amdgpu_crtc->encoder);
 		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
@@ -2838,8 +2838,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
 	if (!amdgpu_crtc->adjusted_clock)
 		return -EINVAL;
 
-	if ((adev->asic_type == CHIP_ELLESMERE) ||
-	    (adev->asic_type == CHIP_BAFFIN)) {
+	if ((adev->asic_type == CHIP_POLARIS10) ||
+	    (adev->asic_type == CHIP_POLARIS11)) {
 		struct amdgpu_encoder *amdgpu_encoder =
 			to_amdgpu_encoder(amdgpu_crtc->encoder);
 		int encoder_mode =
@@ -3004,12 +3004,12 @@ static int dce_v11_0_early_init(void *handle)
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 9;
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		adev->mode_info.num_crtc = 6;
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		adev->mode_info.num_crtc = 5;
 		adev->mode_info.num_hpd = 5;
 		adev->mode_info.num_dig = 5;
@@ -3116,8 +3116,8 @@ static int dce_v11_0_hw_init(void *handle)
 	/* init dig PHYs, disp eng pll */
 	amdgpu_atombios_crtc_powergate_init(adev);
 	amdgpu_atombios_encoder_init_dig(adev);
-	if ((adev->asic_type == CHIP_ELLESMERE) ||
-	    (adev->asic_type == CHIP_BAFFIN)) {
+	if ((adev->asic_type == CHIP_POLARIS10) ||
+	    (adev->asic_type == CHIP_POLARIS11)) {
 		amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
 						   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
 		amdgpu_atombios_crtc_set_dce_clock(adev, 0,

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

@@ -52,7 +52,7 @@
 
 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
-#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002
+#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
 
 #define ARRAY_MODE(x)					((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
@@ -121,19 +121,19 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
 
-MODULE_FIRMWARE("amdgpu/baffin_ce.bin");
-MODULE_FIRMWARE("amdgpu/baffin_pfp.bin");
-MODULE_FIRMWARE("amdgpu/baffin_me.bin");
-MODULE_FIRMWARE("amdgpu/baffin_mec.bin");
-MODULE_FIRMWARE("amdgpu/baffin_mec2.bin");
-MODULE_FIRMWARE("amdgpu/baffin_rlc.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
 
-MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_me.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
 
 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
 {
@@ -265,7 +265,7 @@ static const u32 tonga_mgcg_cgcg_init[] =
 	mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 };
 
-static const u32 golden_settings_baffin_a11[] =
+static const u32 golden_settings_polaris11_a11[] =
 {
 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 	mmDB_DEBUG2, 0xf00fffff, 0x00000400,
@@ -281,7 +281,7 @@ static const u32 golden_settings_baffin_a11[] =
 	mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
 };
 
-static const u32 baffin_golden_common_all[] =
+static const u32 polaris11_golden_common_all[] =
 {
 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
@@ -293,7 +293,7 @@ static const u32 baffin_golden_common_all[] =
 	mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
 };
 
-static const u32 golden_settings_ellesmere_a11[] =
+static const u32 golden_settings_polaris10_a11[] =
 {
 	mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
 	mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
@@ -311,7 +311,7 @@ static const u32 golden_settings_ellesmere_a11[] =
 	mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 };
 
-static const u32 ellesmere_golden_common_all[] =
+static const u32 polaris10_golden_common_all[] =
 {
 	mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 	mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
@@ -674,21 +674,21 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 						 tonga_golden_common_all,
 						 (const u32)ARRAY_SIZE(tonga_golden_common_all));
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		amdgpu_program_register_sequence(adev,
-						 golden_settings_baffin_a11,
-						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
+						 golden_settings_polaris11_a11,
+						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 		amdgpu_program_register_sequence(adev,
-						 baffin_golden_common_all,
-						 (const u32)ARRAY_SIZE(baffin_golden_common_all));
+						 polaris11_golden_common_all,
+						 (const u32)ARRAY_SIZE(polaris11_golden_common_all));
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		amdgpu_program_register_sequence(adev,
-						 golden_settings_ellesmere_a11,
-						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
+						 golden_settings_polaris10_a11,
+						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 		amdgpu_program_register_sequence(adev,
-						 ellesmere_golden_common_all,
-						 (const u32)ARRAY_SIZE(ellesmere_golden_common_all));
+						 polaris10_golden_common_all,
+						 (const u32)ARRAY_SIZE(polaris10_golden_common_all));
 		break;
 	case CHIP_CARRIZO:
 		amdgpu_program_register_sequence(adev,
@@ -859,11 +859,11 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 	case CHIP_FIJI:
 		chip_name = "fiji";
 		break;
-	case CHIP_BAFFIN:
-		chip_name = "baffin";
+	case CHIP_POLARIS11:
+		chip_name = "polaris11";
 		break;
-	case CHIP_ELLESMERE:
-		chip_name = "ellesmere";
+	case CHIP_POLARIS10:
+		chip_name = "polaris10";
 		break;
 	case CHIP_STONEY:
 		chip_name = "stoney";
@@ -1092,11 +1092,11 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
 			PACKET3_SET_CONTEXT_REG_START);
 	switch (adev->asic_type) {
 	case CHIP_TONGA:
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		buffer[count++] = cpu_to_le32(0x16000012);
 		buffer[count++] = cpu_to_le32(0x0000002A);
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		buffer[count++] = cpu_to_le32(0x16000012);
 		buffer[count++] = cpu_to_le32(0x00000000);
 		break;
@@ -1628,7 +1628,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 		gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		ret = amdgpu_atombios_get_gfx_info(adev);
 		if (ret)
 			return ret;
@@ -1640,9 +1640,9 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-		gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN;
+		gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		ret = amdgpu_atombios_get_gfx_info(adev);
 		if (ret)
 			return ret;
@@ -2551,7 +2551,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
 
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 				PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -2753,7 +2753,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
 				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
 
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 				PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 				TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
@@ -3658,7 +3658,7 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
 	WREG32(mmRLC_SRM_CNTL, data);
 }
 
-static void baffin_init_power_gating(struct amdgpu_device *adev)
+static void polaris11_init_power_gating(struct amdgpu_device *adev)
 {
 	uint32_t data;
 
@@ -3701,8 +3701,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
 		gfx_v8_0_init_save_restore_list(adev);
 		gfx_v8_0_enable_save_restore_machine(adev);
 
-		if (adev->asic_type == CHIP_BAFFIN)
-			baffin_init_power_gating(adev);
+		if (adev->asic_type == CHIP_POLARIS11)
+			polaris11_init_power_gating(adev);
 	}
 }
 
@@ -3776,8 +3776,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
 
 	/* disable CG */
 	WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
-	if (adev->asic_type == CHIP_BAFFIN ||
-		adev->asic_type == CHIP_ELLESMERE)
+	if (adev->asic_type == CHIP_POLARIS11 ||
+		adev->asic_type == CHIP_POLARIS10)
 		WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
 
 	/* disable PG */
@@ -3958,11 +3958,11 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
 	amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
 	switch (adev->asic_type) {
 	case CHIP_TONGA:
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		amdgpu_ring_write(ring, 0x16000012);
 		amdgpu_ring_write(ring, 0x0000002A);
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		amdgpu_ring_write(ring, 0x16000012);
 		amdgpu_ring_write(ring, 0x00000000);
 		break;
@@ -4610,8 +4610,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
 			if ((adev->asic_type == CHIP_CARRIZO) ||
 			    (adev->asic_type == CHIP_FIJI) ||
 			    (adev->asic_type == CHIP_STONEY) ||
-			    (adev->asic_type == CHIP_BAFFIN) ||
-			    (adev->asic_type == CHIP_ELLESMERE)) {
+			    (adev->asic_type == CHIP_POLARIS11) ||
+			    (adev->asic_type == CHIP_POLARIS10)) {
 				WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
 				       AMDGPU_DOORBELL_KIQ << 2);
 				WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
@@ -4646,8 +4646,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
 		WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
 		mqd->cp_hqd_persistent_state = tmp;
 		if (adev->asic_type == CHIP_STONEY ||
-			adev->asic_type == CHIP_BAFFIN ||
-			adev->asic_type == CHIP_ELLESMERE) {
+			adev->asic_type == CHIP_POLARIS11 ||
+			adev->asic_type == CHIP_POLARIS10) {
 			tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL);
 			tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1);
 			WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp);
@@ -5216,7 +5216,7 @@ static int gfx_v8_0_late_init(void *handle)
 	return 0;
 }
 
-static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
+static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
 		bool enable)
 {
 	uint32_t data, temp;
@@ -5242,7 +5242,7 @@ static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
 	}
 }
 
-static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
+static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
 		bool enable)
 {
 	uint32_t data, temp;
@@ -5263,7 +5263,7 @@ static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev
 	}
 }
 
-static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
+static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
 		bool enable)
 {
 	uint32_t data, temp;
@@ -5293,15 +5293,15 @@ static int gfx_v8_0_set_powergating_state(void *handle,
 		return 0;
 
 	switch (adev->asic_type) {
-	case CHIP_BAFFIN:
-		if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG)
-			baffin_enable_gfx_static_mg_power_gating(adev,
+	case CHIP_POLARIS11:
+		if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)
+			polaris11_enable_gfx_static_mg_power_gating(adev,
 					state == AMD_PG_STATE_GATE ? true : false);
-		else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG)
-			baffin_enable_gfx_dynamic_mg_power_gating(adev,
+		else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)
+			polaris11_enable_gfx_dynamic_mg_power_gating(adev,
 					state == AMD_PG_STATE_GATE ? true : false);
 		else
-			baffin_enable_gfx_quick_mg_power_gating(adev,
+			polaris11_enable_gfx_quick_mg_power_gating(adev,
 					state == AMD_PG_STATE_GATE ? true : false);
 		break;
 	default:

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

@@ -43,8 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 
 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
-MODULE_FIRMWARE("amdgpu/baffin_mc.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
 
 static const u32 golden_settings_tonga_a11[] =
 {
@@ -75,7 +75,7 @@ static const u32 fiji_mgcg_cgcg_init[] =
 	mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 };
 
-static const u32 golden_settings_baffin_a11[] =
+static const u32 golden_settings_polaris11_a11[] =
 {
 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
 	mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
@@ -83,7 +83,7 @@ static const u32 golden_settings_baffin_a11[] =
 	mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
 };
 
-static const u32 golden_settings_ellesmere_a11[] =
+static const u32 golden_settings_polaris10_a11[] =
 {
 	mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
 	mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
@@ -122,15 +122,15 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 						 golden_settings_tonga_a11,
 						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		amdgpu_program_register_sequence(adev,
-						 golden_settings_baffin_a11,
-						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
+						 golden_settings_polaris11_a11,
+						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		amdgpu_program_register_sequence(adev,
-						 golden_settings_ellesmere_a11,
-						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
+						 golden_settings_polaris10_a11,
+						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 		break;
 	case CHIP_CARRIZO:
 		amdgpu_program_register_sequence(adev,
@@ -238,11 +238,11 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
 	case CHIP_TONGA:
 		chip_name = "tonga";
 		break;
-	case CHIP_BAFFIN:
-		chip_name = "baffin";
+	case CHIP_POLARIS11:
+		chip_name = "polaris11";
 		break;
-	case CHIP_ELLESMERE:
-		chip_name = "ellesmere";
+	case CHIP_POLARIS10:
+		chip_name = "polaris10";
 		break;
 	case CHIP_FIJI:
 	case CHIP_CARRIZO:

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

@@ -56,10 +56,10 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin");
-MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin");
-MODULE_FIRMWARE("amdgpu/baffin_sdma.bin");
-MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
+MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
+MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
 
 
 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
@@ -106,7 +106,7 @@ static const u32 fiji_mgcg_cgcg_init[] =
 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 };
 
-static const u32 golden_settings_baffin_a11[] =
+static const u32 golden_settings_polaris11_a11[] =
 {
 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 	mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
@@ -118,7 +118,7 @@ static const u32 golden_settings_baffin_a11[] =
 	mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 };
 
-static const u32 golden_settings_ellesmere_a11[] =
+static const u32 golden_settings_polaris10_a11[] =
 {
 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
@@ -203,15 +203,15 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 						 golden_settings_tonga_a11,
 						 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		amdgpu_program_register_sequence(adev,
-						 golden_settings_baffin_a11,
-						 (const u32)ARRAY_SIZE(golden_settings_baffin_a11));
+						 golden_settings_polaris11_a11,
+						 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		amdgpu_program_register_sequence(adev,
-						 golden_settings_ellesmere_a11,
-						 (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11));
+						 golden_settings_polaris10_a11,
+						 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
 		break;
 	case CHIP_CARRIZO:
 		amdgpu_program_register_sequence(adev,
@@ -261,11 +261,11 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 	case CHIP_FIJI:
 		chip_name = "fiji";
 		break;
-	case CHIP_BAFFIN:
-		chip_name = "baffin";
+	case CHIP_POLARIS11:
+		chip_name = "polaris11";
 		break;
-	case CHIP_ELLESMERE:
-		chip_name = "ellesmere";
+	case CHIP_POLARIS10:
+		chip_name = "polaris10";
 		break;
 	case CHIP_CARRIZO:
 		chip_name = "carrizo";

drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

@@ -315,11 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
 {
 	u32 tmp;
 
-	/* Fiji, Stoney, Ellesmere, Baffin are single pipe */
+	/* Fiji, Stoney, Polaris10, Polaris11 are single pipe */
 	if ((adev->asic_type == CHIP_FIJI) ||
 	    (adev->asic_type == CHIP_STONEY) ||
-	    (adev->asic_type == CHIP_ELLESMERE) ||
-	    (adev->asic_type == CHIP_BAFFIN))
+	    (adev->asic_type == CHIP_POLARIS10) ||
+	    (adev->asic_type == CHIP_POLARIS11))
 		return AMDGPU_VCE_HARVEST_VCE1;
 
 	/* Tonga and CZ are dual or single pipe */

drivers/gpu/drm/amd/amdgpu/vi.c

@@ -276,8 +276,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
 						 stoney_mgcg_cgcg_init,
 						 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 		break;
-	case CHIP_BAFFIN:
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS11:
+	case CHIP_POLARIS10:
 	default:
 		break;
 	}
@@ -539,8 +539,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 		break;
 	case CHIP_FIJI:
 	case CHIP_TONGA:
-	case CHIP_BAFFIN:
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS11:
+	case CHIP_POLARIS10:
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
 		asic_register_table = cz_allowed_read_registers;
@@ -911,7 +911,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
 	},
 };
 
-static const struct amdgpu_ip_block_version baffin_ip_blocks[] =
+static const struct amdgpu_ip_block_version polaris11_ip_blocks[] =
 {
 	/* ORDER MATTERS! */
 	{
@@ -1071,10 +1071,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
 		adev->ip_blocks = tonga_ip_blocks;
 		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
 		break;
-	case CHIP_BAFFIN:
-	case CHIP_ELLESMERE:
-		adev->ip_blocks = baffin_ip_blocks;
-		adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks);
+	case CHIP_POLARIS11:
+	case CHIP_POLARIS10:
+		adev->ip_blocks = polaris11_ip_blocks;
+		adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks);
 		break;
 	case CHIP_CARRIZO:
 	case CHIP_STONEY:
@@ -1177,12 +1177,12 @@ static int vi_common_early_init(void *handle)
 		adev->pg_flags = 0;
 		adev->external_rev_id = adev->rev_id + 0x14;
 		break;
-	case CHIP_BAFFIN:
+	case CHIP_POLARIS11:
 		adev->cg_flags = 0;
 		adev->pg_flags = 0;
 		adev->external_rev_id = adev->rev_id + 0x5A;
 		break;
-	case CHIP_ELLESMERE:
+	case CHIP_POLARIS10:
 		adev->cg_flags = 0;
 		adev->pg_flags = 0;
 		adev->external_rev_id = adev->rev_id + 0x50;

drivers/gpu/drm/amd/include/amd_shared.h

@@ -48,8 +48,8 @@ enum amd_asic_type {
 	CHIP_FIJI,
 	CHIP_CARRIZO,
 	CHIP_STONEY,
-	CHIP_ELLESMERE,
-	CHIP_BAFFIN,
+	CHIP_POLARIS10,
+	CHIP_POLARIS11,
 	CHIP_LAST,
 };
 

drivers/gpu/drm/amd/include/atombios.h

@@ -2061,7 +2061,7 @@ typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1
 #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS         0x01
 #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK           0x02
 
-// SetDCEClockTable input parameter for DCE11.2( ELM and BF ) and above
+// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above
 typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1
 {
   ULONG  ulDCEClkFreq;                               // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
@@ -5494,7 +5494,7 @@ typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_4
   ULONG ulReserved[8];            // Reserved for future ASIC
 }ATOM_ASIC_PROFILING_INFO_V3_4;
 
-// for Ellemser/Baffin speed EVV algorithm
+// for  Polaris10/Polaris11 speed EVV algorithm
 typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_5
 {
   ATOM_COMMON_TABLE_HEADER         asHeader;
@@ -5549,7 +5549,7 @@ typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{
 }ATOM_SCLK_FCW_RANGE_ENTRY_V1;
 
 
-// SMU_InfoTable for Ellesmere/Baffin
+// SMU_InfoTable for  Polaris10/Polaris11
 typedef struct  _ATOM_SMU_INFO_V2_1
 {
   ATOM_COMMON_TABLE_HEADER         asHeader;

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

@@ -9,8 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
                tonga_hwmgr.o pppcielanes.o  tonga_thermal.o\
                fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
                fiji_clockpowergating.o fiji_thermal.o \
-	       ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \
-	       ellesmere_clockpowergating.o
+	       polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \
+	       polaris10_clockpowergating.o
 
 AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))
 

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

@@ -34,7 +34,7 @@
 extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr);
-extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
+extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
 
 int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
 {
@@ -68,9 +68,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
 		case CHIP_FIJI:
 			fiji_hwmgr_init(hwmgr);
 			break;
-		case CHIP_BAFFIN:
-		case CHIP_ELLESMERE:
-			ellesemere_hwmgr_init(hwmgr);
+		case CHIP_POLARIS11:
+		case CHIP_POLARIS10:
+			polaris10_hwmgr_init(hwmgr);
 			break;
 		default:
 			return -EINVAL;

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c

@@ -21,9 +21,9 @@
  *
  */
 
-#include "ellesmere_clockpowergating.h"
+#include "polaris10_clockpowergating.h"
 
-int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
+int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_uvd_power_gating(hwmgr))
 		return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -31,7 +31,7 @@ int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
+int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_uvd_power_gating(hwmgr)) {
 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -47,7 +47,7 @@ int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
+int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_vce_power_gating(hwmgr))
 		return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -55,7 +55,7 @@ int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
+int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cf_want_vce_power_gating(hwmgr))
 		return smum_send_msg_to_smc(hwmgr->smumgr,
@@ -63,7 +63,7 @@ int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
+int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_SamuPowerGating))
@@ -72,7 +72,7 @@ int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
+int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr)
 {
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_SamuPowerGating))
@@ -81,24 +81,24 @@ int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
+int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	data->uvd_power_gated = false;
 	data->vce_power_gated = false;
 	data->samu_power_gated = false;
 
-	ellesmere_phm_powerup_uvd(hwmgr);
-	ellesmere_phm_powerup_vce(hwmgr);
-	ellesmere_phm_powerup_samu(hwmgr);
+	polaris10_phm_powerup_uvd(hwmgr);
+	polaris10_phm_powerup_vce(hwmgr);
+	polaris10_phm_powerup_samu(hwmgr);
 
 	return 0;
 }
 
-int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
+int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	if (data->uvd_power_gated == bgate)
 		return 0;
@@ -106,34 +106,34 @@ int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
 	data->uvd_power_gated = bgate;
 
 	if (bgate) {
-		ellesmere_update_uvd_dpm(hwmgr, true);
-		ellesmere_phm_powerdown_uvd(hwmgr);
+		polaris10_update_uvd_dpm(hwmgr, true);
+		polaris10_phm_powerdown_uvd(hwmgr);
 	} else {
-		ellesmere_phm_powerup_uvd(hwmgr);
-		ellesmere_update_uvd_dpm(hwmgr, false);
+		polaris10_phm_powerup_uvd(hwmgr);
+		polaris10_update_uvd_dpm(hwmgr, false);
 	}
 
 	return 0;
 }
 
-int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
+int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	if (data->vce_power_gated == bgate)
 		return 0;
 
 	if (bgate)
-		ellesmere_phm_powerdown_vce(hwmgr);
+		polaris10_phm_powerdown_vce(hwmgr);
 	else
-		ellesmere_phm_powerup_vce(hwmgr);
+		polaris10_phm_powerup_vce(hwmgr);
 
 	return 0;
 }
 
-int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
+int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	if (data->samu_power_gated == bgate)
 		return 0;
@@ -141,17 +141,17 @@ int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate)
 	data->samu_power_gated = bgate;
 
 	if (bgate) {
-		ellesmere_update_samu_dpm(hwmgr, true);
-		ellesmere_phm_powerdown_samu(hwmgr);
+		polaris10_update_samu_dpm(hwmgr, true);
+		polaris10_phm_powerdown_samu(hwmgr);
 	} else {
-		ellesmere_phm_powerup_samu(hwmgr);
-		ellesmere_update_samu_dpm(hwmgr, false);
+		polaris10_phm_powerup_samu(hwmgr);
+		polaris10_update_samu_dpm(hwmgr, false);
 	}
 
 	return 0;
 }
 
-int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
+int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
 					const uint32_t *msg_id)
 {
 	PPSMC_Msg msg;
@@ -399,11 +399,11 @@ int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
-/* This function is for Baffin only for now,
+/* This function is for Polaris11 only for now,
  * Powerplay will only control the static per CU Power Gating.
  * Dynamic per CU Power Gating will be done in gfx.
  */
-int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
+int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable)
 {
 	struct cgs_system_info sys_info = {0};
 	uint32_t active_cus;

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h

@@ -21,20 +21,20 @@
  *
  */
 
-#ifndef _ELLESMERE_CLOCK_POWER_GATING_H_
-#define _ELLESMERE_CLOCK_POWER_GATING_H_
+#ifndef _POLARIS10_CLOCK_POWER_GATING_H_
+#define _POLARIS10_CLOCK_POWER_GATING_H_
 
-#include "ellesmere_hwmgr.h"
+#include "polaris10_hwmgr.h"
 #include "pp_asicblocks.h"
 
-int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
-int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
-int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
-int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
-int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
-int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
-int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
+int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
+int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
+int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
+int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate);
+int polaris10_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
+int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
+int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
 					const uint32_t *msg_id);
-int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
+int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable);
 
-#endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */
+#endif /* _POLARIS10_CLOCK_POWER_GATING_H_ */

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h

@@ -21,42 +21,42 @@
  *
  */
 
-#ifndef ELLESMERE_DYN_DEFAULTS_H
-#define ELLESMERE_DYN_DEFAULTS_H
+#ifndef POLARIS10_DYN_DEFAULTS_H
+#define POLARIS10_DYN_DEFAULTS_H
 
 
-enum Ellesmeredpm_TrendDetection {
-	EllesmereAdpm_TrendDetection_AUTO,
-	EllesmereAdpm_TrendDetection_UP,
-	EllesmereAdpm_TrendDetection_DOWN
+enum Polaris10dpm_TrendDetection {
+	Polaris10Adpm_TrendDetection_AUTO,
+	Polaris10Adpm_TrendDetection_UP,
+	Polaris10Adpm_TrendDetection_DOWN
 };
-typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection;
+typedef enum Polaris10dpm_TrendDetection Polaris10dpm_TrendDetection;
 
 /*  We need to fill in the default values */
 
 
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1              0x000400
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033
-#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0              0x3FFFC102
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1              0x000400
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2              0xC00080
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3              0xC00200
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4              0xC01680
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5              0xC00033
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6              0xC00033
+#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7              0x3FFFC000
 
 
-#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT            0x200
-#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT        0
-#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT            0x00C8
-#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200
-#define PPELLESMERE_REFERENCEDIVIDER_DFLT                  4
+#define PPPOLARIS10_THERMALPROTECTCOUNTER_DFLT            0x200
+#define PPPOLARIS10_STATICSCREENTHRESHOLDUNIT_DFLT        0
+#define PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT            0x00C8
+#define PPPOLARIS10_GFXIDLECLOCKSTOPTHRESHOLD_DFLT        0x200
+#define PPPOLARIS10_REFERENCEDIVIDER_DFLT                  4
 
-#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT             1687
+#define PPPOLARIS10_ULVVOLTAGECHANGEDELAY_DFLT             1687
 
-#define PPELLESMERE_CGULVPARAMETER_DFLT                    0x00040035
-#define PPELLESMERE_CGULVCONTROL_DFLT                      0x00007450
-#define PPELLESMERE_TARGETACTIVITY_DFLT                     50
-#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT                10
+#define PPPOLARIS10_CGULVPARAMETER_DFLT                    0x00040035
+#define PPPOLARIS10_CGULVCONTROL_DFLT                      0x00007450
+#define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
+#define PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT                10
 
 #endif
 

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h

@@ -21,81 +21,81 @@
  *
  */
 
-#ifndef ELLESMERE_HWMGR_H
-#define ELLESMERE_HWMGR_H
+#ifndef POLARIS10_HWMGR_H
+#define POLARIS10_HWMGR_H
 
 #include "hwmgr.h"
 #include "smu74.h"
 #include "smu74_discrete.h"
 #include "ppatomctrl.h"
-#include "ellesmere_ppsmc.h"
-#include "ellesmere_powertune.h"
+#include "polaris10_ppsmc.h"
+#include "polaris10_powertune.h"
 
-#define ELLESMERE_MAX_HARDWARE_POWERLEVELS	2
+#define POLARIS10_MAX_HARDWARE_POWERLEVELS	2
 
-#define ELLESMERE_VOLTAGE_CONTROL_NONE                   0x0
-#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO                0x1
-#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2               0x2
-#define ELLESMERE_VOLTAGE_CONTROL_MERGED                 0x3
+#define POLARIS10_VOLTAGE_CONTROL_NONE                   0x0
+#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO                0x1
+#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2               0x2
+#define POLARIS10_VOLTAGE_CONTROL_MERGED                 0x3
 
 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
 #define DPMTABLE_UPDATE_SCLK        0x00000004
 #define DPMTABLE_UPDATE_MCLK        0x00000008
 
-struct ellesmere_performance_level {
+struct polaris10_performance_level {
 	uint32_t  memory_clock;
 	uint32_t  engine_clock;
 	uint16_t  pcie_gen;
 	uint16_t  pcie_lane;
 };
 
-struct ellesmere_uvd_clocks {
+struct polaris10_uvd_clocks {
 	uint32_t  vclk;
 	uint32_t  dclk;
 };
 
-struct ellesmere_vce_clocks {
+struct polaris10_vce_clocks {
 	uint32_t  evclk;
 	uint32_t  ecclk;
 };
 
-struct ellesmere_power_state {
+struct polaris10_power_state {
 	uint32_t                  magic;
-	struct ellesmere_uvd_clocks    uvd_clks;
-	struct ellesmere_vce_clocks    vce_clks;
+	struct polaris10_uvd_clocks    uvd_clks;
+	struct polaris10_vce_clocks    vce_clks;
 	uint32_t                  sam_clk;
 	uint16_t                  performance_level_count;
 	bool                      dc_compatible;
 	uint32_t                  sclk_threshold;
-	struct ellesmere_performance_level  performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS];
+	struct polaris10_performance_level  performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS];
 };
 
-struct ellesmere_dpm_level {
+struct polaris10_dpm_level {
 	bool	enabled;
 	uint32_t	value;
 	uint32_t	param1;
 };
 
-#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5
+#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5
 #define MAX_REGULAR_DPM_NUMBER 8
-#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500
+#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500
 
-struct ellesmere_single_dpm_table {
+struct polaris10_single_dpm_table {
 	uint32_t		count;
-	struct ellesmere_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
+	struct polaris10_dpm_level	dpm_levels[MAX_REGULAR_DPM_NUMBER];
 };
 
-struct ellesmere_dpm_table {
-	struct ellesmere_single_dpm_table  sclk_table;
-	struct ellesmere_single_dpm_table  mclk_table;
-	struct ellesmere_single_dpm_table  pcie_speed_table;
-	struct ellesmere_single_dpm_table  vddc_table;
-	struct ellesmere_single_dpm_table  vddci_table;
-	struct ellesmere_single_dpm_table  mvdd_table;
+struct polaris10_dpm_table {
+	struct polaris10_single_dpm_table  sclk_table;
+	struct polaris10_single_dpm_table  mclk_table;
+	struct polaris10_single_dpm_table  pcie_speed_table;
+	struct polaris10_single_dpm_table  vddc_table;
+	struct polaris10_single_dpm_table  vddci_table;
+	struct polaris10_single_dpm_table  mvdd_table;
 };
 
-struct ellesmere_clock_registers {
+struct polaris10_clock_registers {
 	uint32_t  vCG_SPLL_FUNC_CNTL;
 	uint32_t  vCG_SPLL_FUNC_CNTL_2;
 	uint32_t  vCG_SPLL_FUNC_CNTL_3;
@@ -116,19 +116,19 @@ struct ellesmere_clock_registers {
 #define DISABLE_MC_LOADMICROCODE   1
 #define DISABLE_MC_CFGPROGRAMMING  2
 
-struct ellesmere_voltage_smio_registers {
+struct polaris10_voltage_smio_registers {
 	uint32_t vS0_VID_LOWER_SMIO_CNTL;
 };
 
-#define ELLESMERE_MAX_LEAKAGE_COUNT  8
+#define POLARIS10_MAX_LEAKAGE_COUNT  8
 
-struct ellesmere_leakage_voltage {
+struct polaris10_leakage_voltage {
 	uint16_t  count;
-	uint16_t  leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT];
-	uint16_t  actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT];
+	uint16_t  leakage_id[POLARIS10_MAX_LEAKAGE_COUNT];
+	uint16_t  actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT];
 };
 
-struct ellesmere_vbios_boot_state {
+struct polaris10_vbios_boot_state {
 	uint16_t    mvdd_bootup_value;
 	uint16_t    vddc_bootup_value;
 	uint16_t    vddci_bootup_value;
@@ -139,19 +139,19 @@ struct ellesmere_vbios_boot_state {
 };
 
 /* Ultra Low Voltage parameter structure */
-struct ellesmere_ulv_parm {
+struct polaris10_ulv_parm {
 	bool                           ulv_supported;
 	uint32_t                       cg_ulv_parameter;
 	uint32_t                       ulv_volt_change_delay;
-	struct ellesmere_performance_level  ulv_power_level;
+	struct polaris10_performance_level  ulv_power_level;
 };
 
-struct ellesmere_display_timing {
+struct polaris10_display_timing {
 	uint32_t  min_clock_in_sr;
 	uint32_t  num_existing_displays;
 };
 
-struct ellesmere_dpmlevel_enable_mask {
+struct polaris10_dpmlevel_enable_mask {
 	uint32_t  uvd_dpm_enable_mask;
 	uint32_t  vce_dpm_enable_mask;
 	uint32_t  acp_dpm_enable_mask;
@@ -161,22 +161,22 @@ struct ellesmere_dpmlevel_enable_mask {
 	uint32_t  pcie_dpm_enable_mask;
 };
 
-struct ellesmere_pcie_perf_range {
+struct polaris10_pcie_perf_range {
 	uint16_t  max;
 	uint16_t  min;
 };
-struct ellesmere_range_table {
+struct polaris10_range_table {
 	uint32_t trans_lower_frequency; /* in 10khz */
 	uint32_t trans_upper_frequency;
 };
 
-struct ellesmere_hwmgr {
-	struct ellesmere_dpm_table			dpm_table;
-	struct ellesmere_dpm_table			golden_dpm_table;
+struct polaris10_hwmgr {
+	struct polaris10_dpm_table			dpm_table;
+	struct polaris10_dpm_table			golden_dpm_table;
 	SMU74_Discrete_DpmTable				smc_state_table;
 	struct SMU74_Discrete_Ulv            ulv_setting;
 
-	struct ellesmere_range_table                range_table[NUM_SCLK_RANGE];
+	struct polaris10_range_table                range_table[NUM_SCLK_RANGE];
 	uint32_t						voting_rights_clients0;
 	uint32_t						voting_rights_clients1;
 	uint32_t						voting_rights_clients2;
@@ -192,8 +192,8 @@ struct ellesmere_hwmgr {
 
 	uint32_t						active_auto_throttle_sources;
 
-	struct ellesmere_clock_registers            clock_registers;
-	struct ellesmere_voltage_smio_registers      voltage_smio_registers;
+	struct polaris10_clock_registers            clock_registers;
+	struct polaris10_voltage_smio_registers      voltage_smio_registers;
 
 	bool                           is_memory_gddr5;
 	uint16_t                       acpi_vddc;
@@ -203,8 +203,8 @@ struct ellesmere_hwmgr {
 	uint32_t                       pcie_gen_cap;
 	uint32_t                       pcie_lane_cap;
 	uint32_t                       pcie_spc_cap;
-	struct ellesmere_leakage_voltage          vddc_leakage;
-	struct ellesmere_leakage_voltage          Vddci_leakage;
+	struct polaris10_leakage_voltage          vddc_leakage;
+	struct polaris10_leakage_voltage          Vddci_leakage;
 
 	uint32_t                             mvdd_control;
 	uint32_t                             vddc_mask_low;
@@ -218,7 +218,7 @@ struct ellesmere_hwmgr {
 	uint32_t                             mclk_edc_enable_threshold;
 	uint32_t                             mclk_edcwr_enable_threshold;
 	bool                                is_uvd_enabled;
-	struct ellesmere_vbios_boot_state        vbios_boot_state;
+	struct polaris10_vbios_boot_state        vbios_boot_state;
 
 	bool                           pcie_performance_request;
 	bool                           battery_state;
@@ -250,7 +250,7 @@ struct ellesmere_hwmgr {
 	bool                                 performance_request_registered;
 
 	/* ---- Low Power Features ---- */
-	struct ellesmere_ulv_parm                 ulv;
+	struct polaris10_ulv_parm                 ulv;
 
 	/* ---- CAC Stuff ---- */
 	uint32_t                       cac_table_start;
@@ -264,7 +264,7 @@ struct ellesmere_hwmgr {
 	bool                           enable_tdc_limit_feature;
 	bool                           enable_pkg_pwr_tracking_feature;
 	bool                           disable_uvd_power_tune_feature;
-	struct ellesmere_pt_defaults       *power_tune_defaults;
+	struct polaris10_pt_defaults       *power_tune_defaults;
 	struct SMU74_Discrete_PmFuses  power_tune_table;
 	uint32_t                       dte_tj_offset;
 	uint32_t                       fast_watermark_threshold;
@@ -273,20 +273,20 @@ struct ellesmere_hwmgr {
 	bool                           vddc_phase_shed_control;
 
 	/* ---- DI/DT ---- */
-	struct ellesmere_display_timing        display_timing;
+	struct polaris10_display_timing        display_timing;
 	uint32_t                      bif_sclk_table[SMU74_MAX_LEVELS_LINK];
 
 	/* ---- Thermal Temperature Setting ---- */
-	struct ellesmere_dpmlevel_enable_mask     dpm_level_enable_mask;
+	struct polaris10_dpmlevel_enable_mask     dpm_level_enable_mask;
 	uint32_t                                  need_update_smu7_dpm_table;
 	uint32_t                                  sclk_dpm_key_disabled;
 	uint32_t                                  mclk_dpm_key_disabled;
 	uint32_t                                  pcie_dpm_key_disabled;
 	uint32_t                                  min_engine_clocks;
-	struct ellesmere_pcie_perf_range          pcie_gen_performance;
-	struct ellesmere_pcie_perf_range          pcie_lane_performance;
-	struct ellesmere_pcie_perf_range          pcie_gen_power_saving;
-	struct ellesmere_pcie_perf_range          pcie_lane_power_saving;
+	struct polaris10_pcie_perf_range          pcie_gen_performance;
+	struct polaris10_pcie_perf_range          pcie_lane_performance;
+	struct polaris10_pcie_perf_range          pcie_gen_power_saving;
+	struct polaris10_pcie_perf_range          pcie_lane_power_saving;
 	bool                                      use_pcie_performance_levels;
 	bool                                      use_pcie_power_saving_levels;
 	uint32_t                                  activity_target[SMU74_MAX_LEVELS_GRAPHICS];
@@ -312,43 +312,43 @@ struct ellesmere_hwmgr {
 };
 
 /* To convert to Q8.8 format for firmware */
-#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT             256
-
-enum Ellesmere_I2CLineID {
-	Ellesmere_I2CLineID_DDC1 = 0x90,
-	Ellesmere_I2CLineID_DDC2 = 0x91,
-	Ellesmere_I2CLineID_DDC3 = 0x92,
-	Ellesmere_I2CLineID_DDC4 = 0x93,
-	Ellesmere_I2CLineID_DDC5 = 0x94,
-	Ellesmere_I2CLineID_DDC6 = 0x95,
-	Ellesmere_I2CLineID_SCLSDA = 0x96,
-	Ellesmere_I2CLineID_DDCVGA = 0x97
+#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT             256
+
+enum Polaris10_I2CLineID {
+	Polaris10_I2CLineID_DDC1 = 0x90,
+	Polaris10_I2CLineID_DDC2 = 0x91,
+	Polaris10_I2CLineID_DDC3 = 0x92,
+	Polaris10_I2CLineID_DDC4 = 0x93,
+	Polaris10_I2CLineID_DDC5 = 0x94,
+	Polaris10_I2CLineID_DDC6 = 0x95,
+	Polaris10_I2CLineID_SCLSDA = 0x96,
+	Polaris10_I2CLineID_DDCVGA = 0x97
 };
 
-#define ELLESMERE_I2C_DDC1DATA          0
-#define ELLESMERE_I2C_DDC1CLK           1
-#define ELLESMERE_I2C_DDC2DATA          2
-#define ELLESMERE_I2C_DDC2CLK           3
-#define ELLESMERE_I2C_DDC3DATA          4
-#define ELLESMERE_I2C_DDC3CLK           5
-#define ELLESMERE_I2C_SDA               40
-#define ELLESMERE_I2C_SCL               41
-#define ELLESMERE_I2C_DDC4DATA          65
-#define ELLESMERE_I2C_DDC4CLK           66
-#define ELLESMERE_I2C_DDC5DATA          0x48
-#define ELLESMERE_I2C_DDC5CLK           0x49
-#define ELLESMERE_I2C_DDC6DATA          0x4a
-#define ELLESMERE_I2C_DDC6CLK           0x4b
-#define ELLESMERE_I2C_DDCVGADATA        0x4c
-#define ELLESMERE_I2C_DDCVGACLK         0x4d
-
-#define ELLESMERE_UNUSED_GPIO_PIN       0x7F
-
-int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr);
-
-int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
-int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
+#define POLARIS10_I2C_DDC1DATA          0
+#define POLARIS10_I2C_DDC1CLK           1
+#define POLARIS10_I2C_DDC2DATA          2
+#define POLARIS10_I2C_DDC2CLK           3
+#define POLARIS10_I2C_DDC3DATA          4
+#define POLARIS10_I2C_DDC3CLK           5
+#define POLARIS10_I2C_SDA               40
+#define POLARIS10_I2C_SCL               41
+#define POLARIS10_I2C_DDC4DATA          65
+#define POLARIS10_I2C_DDC4CLK           66
+#define POLARIS10_I2C_DDC5DATA          0x48
+#define POLARIS10_I2C_DDC5CLK           0x49
+#define POLARIS10_I2C_DDC6DATA          0x4a
+#define POLARIS10_I2C_DDC6CLK           0x4b
+#define POLARIS10_I2C_DDCVGADATA        0x4c
+#define POLARIS10_I2C_DDCVGACLK         0x4d
+
+#define POLARIS10_UNUSED_GPIO_PIN       0x7F
+
+int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
+
+int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
+int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
+int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
 
 #endif
 

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c

@@ -23,16 +23,16 @@
 
 #include "hwmgr.h"
 #include "smumgr.h"
-#include "ellesmere_hwmgr.h"
-#include "ellesmere_powertune.h"
-#include "ellesmere_smumgr.h"
+#include "polaris10_hwmgr.h"
+#include "polaris10_powertune.h"
+#include "polaris10_smumgr.h"
 #include "smu74_discrete.h"
 #include "pp_debug.h"
 
 #define VOLTAGE_SCALE  4
 #define POWERTUNE_DEFAULT_SET_MAX    1
 
-struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
+struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
 	/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
 	 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
 	{ 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
@@ -40,27 +40,27 @@ struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAU
 	{ 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
 };
 
-void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
+void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *ellesmere_hwmgr = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *polaris10_hwmgr = (struct polaris10_hwmgr *)(hwmgr->backend);
 	struct  phm_ppt_v1_information *table_info =
 			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
 
 	if (table_info &&
 			table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
 			table_info->cac_dtp_table->usPowerTuneDataSetID)
-		ellesmere_hwmgr->power_tune_defaults =
-				&ellesmere_power_tune_data_set_array
+		polaris10_hwmgr->power_tune_defaults =
+				&polaris10_power_tune_data_set_array
 				[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
 	else
-		ellesmere_hwmgr->power_tune_defaults = &ellesmere_power_tune_data_set_array[0];
+		polaris10_hwmgr->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
 
 }
 
-int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
+int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
 	SMU74_Discrete_DpmTable  *dpm_table = &(data->smc_state_table);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -101,10 +101,10 @@ int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
 
 	data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
 	data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
@@ -114,13 +114,13 @@ static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 {
 	uint16_t tdc_limit;
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
-	struct  ellesmere_pt_defaults *defaults = data->power_tune_defaults;
+	struct  polaris10_pt_defaults *defaults = data->power_tune_defaults;
 
 	tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
 	data->power_tune_table.TDC_VDDC_PkgLimit =
@@ -132,13 +132,13 @@ static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
+static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
-	struct ellesmere_pt_defaults *defaults = data->power_tune_defaults;
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
+	struct polaris10_pt_defaults *defaults = data->power_tune_defaults;
 	uint32_t temp;
 
-	if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+	if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
 			fuse_table_offset +
 			offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
 			(uint32_t *)&temp, data->sram_end))
@@ -156,10 +156,10 @@ static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of
 	return 0;
 }
 
-static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
 {
 	int i;
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	/* Currently not used. Set all to zero. */
 	for (i = 0; i < 16; i++)
@@ -168,9 +168,9 @@ static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
 		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
@@ -182,10 +182,10 @@ static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
 {
 	int i;
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	/* Currently not used. Set all to zero. */
 	for (i = 0; i < 16; i++)
@@ -194,14 +194,14 @@ static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-static int ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
+static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
 {
 	return 0;
 }
 
-static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
+static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
@@ -219,14 +219,14 @@ static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr
 	return 0;
 }
 
-int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
+int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 	uint32_t pm_fuse_table_offset;
 
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_PowerContainment)) {
-		if (ellesmere_read_smc_sram_dword(hwmgr->smumgr,
+		if (polaris10_read_smc_sram_dword(hwmgr->smumgr,
 				SMU7_FIRMWARE_HEADER_LOCATION +
 				offsetof(SMU74_Firmware_Header, PmFuseTable),
 				&pm_fuse_table_offset, data->sram_end))
@@ -234,47 +234,47 @@ int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 					"Attempt to get pm_fuse_table_offset Failed!",
 					return -EINVAL);
 
-		if (ellesmere_populate_svi_load_line(hwmgr))
+		if (polaris10_populate_svi_load_line(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate SviLoadLine Failed!",
 					return -EINVAL);
 
-		if (ellesmere_populate_tdc_limit(hwmgr))
+		if (polaris10_populate_tdc_limit(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate TDCLimit Failed!", return -EINVAL);
 
-		if (ellesmere_populate_dw8(hwmgr, pm_fuse_table_offset))
+		if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate TdcWaterfallCtl, "
 					"LPMLTemperature Min and Max Failed!",
 					return -EINVAL);
 
-		if (0 != ellesmere_populate_temperature_scaler(hwmgr))
+		if (0 != polaris10_populate_temperature_scaler(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate LPMLTemperatureScaler Failed!",
 					return -EINVAL);
 
-		if (ellesmere_populate_fuzzy_fan(hwmgr))
+		if (polaris10_populate_fuzzy_fan(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate Fuzzy Fan Control parameters Failed!",
 					return -EINVAL);
 
-		if (ellesmere_populate_gnb_lpml(hwmgr))
+		if (polaris10_populate_gnb_lpml(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate GnbLPML Failed!",
 					return -EINVAL);
 
-		if (ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
+		if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate GnbLPML Min and Max Vid Failed!",
 					return -EINVAL);
 
-		if (ellesmere_populate_bapm_vddc_base_leakage_sidd(hwmgr))
+		if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
 			PP_ASSERT_WITH_CODE(false,
 					"Attempt to populate BapmVddCBaseLeakage Hi and Lo "
 					"Sidd Failed!", return -EINVAL);
 
-		if (ellesmere_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
+		if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
 				(uint8_t *)&data->power_tune_table,
 				sizeof(struct SMU74_Discrete_PmFuses), data->sram_end))
 			PP_ASSERT_WITH_CODE(false,
@@ -284,9 +284,9 @@ int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
-int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr)
+int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 	int result = 0;
 
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@@ -302,9 +302,9 @@ int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
-int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
+int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
 	if (data->power_containment_features &
 			POWERCONTAINMENT_FEATURE_PkgPwrLimit)
@@ -313,15 +313,15 @@ int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
 	return 0;
 }
 
-static int ellesmere_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
+static int polaris10_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
 {
 	return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
 			PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
 }
 
-int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
+int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr)
 {
-	struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend);
+	struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
 	int smc_result;
@@ -363,7 +363,7 @@ int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
 				data->power_containment_features |=
 						POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 
-				if (ellesmere_set_power_limit(hwmgr, default_limit))
+				if (polaris10_set_power_limit(hwmgr, default_limit))
 					printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
 			}
 		}
@@ -371,7 +371,7 @@ int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr)
 	return result;
 }
 
-int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr)
+int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr)
 {
 	struct phm_ppt_v1_information *table_info =
 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
@@ -389,7 +389,7 @@ int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr)
 		 * but message to be 8 bit fraction for messages
 		 */
 		target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
-		result = ellesmere_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
+		result = polaris10_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
 	}
 
 	return result;

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h

@@ -20,15 +20,15 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  */
-#ifndef ELLESMERE_POWERTUNE_H
-#define ELLESMERE_POWERTUNE_H
+#ifndef POLARIS10_POWERTUNE_H
+#define POLARIS10_POWERTUNE_H
 
-enum ellesmere_pt_config_reg_type {
-	ELLESMERE_CONFIGREG_MMR = 0,
-	ELLESMERE_CONFIGREG_SMC_IND,
-	ELLESMERE_CONFIGREG_DIDT_IND,
-	ELLESMERE_CONFIGREG_CACHE,
-	ELLESMERE_CONFIGREG_MAX
+enum polaris10_pt_config_reg_type {
+	POLARIS10_CONFIGREG_MMR = 0,
+	POLARIS10_CONFIGREG_SMC_IND,
+	POLARIS10_CONFIGREG_DIDT_IND,
+	POLARIS10_CONFIGREG_CACHE,
+	POLARIS10_CONFIGREG_MAX
 };
 
 /* PowerContainment Features */
@@ -36,15 +36,15 @@ enum ellesmere_pt_config_reg_type {
 #define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
 
-struct ellesmere_pt_config_reg {
+struct polaris10_pt_config_reg {
 	uint32_t                           offset;
 	uint32_t                           mask;
 	uint32_t                           shift;
 	uint32_t                           value;
-	enum ellesmere_pt_config_reg_type       type;
+	enum polaris10_pt_config_reg_type       type;
 };
 
-struct ellesmere_pt_defaults {
+struct polaris10_pt_defaults {
 	uint8_t   SviLoadLineEn;
 	uint8_t   SviLoadLineVddC;
 	uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
@@ -58,13 +58,13 @@ struct ellesmere_pt_defaults {
 	uint16_t  BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
 };
 
-void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
-int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
-int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr);
-int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr);
-int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr);
-int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
-int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr);
+void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
+int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
+int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
+int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr);
+int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr);
+int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
+int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr);
 
-#endif  /* ELLESMERE_POWERTUNE_H */
+#endif  /* POLARIS10_POWERTUNE_H */
 

drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h → drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h

@@ -21,41 +21,41 @@
  *
  */
 
-#ifndef _ELLESMERE_THERMAL_H_
-#define _ELLESMERE_THERMAL_H_
+#ifndef _POLARIS10_THERMAL_H_
+#define _POLARIS10_THERMAL_H_
 
 #include "hwmgr.h"
 
-#define ELLESMERE_THERMAL_HIGH_ALERT_MASK         0x1
-#define ELLESMERE_THERMAL_LOW_ALERT_MASK          0x2
+#define POLARIS10_THERMAL_HIGH_ALERT_MASK         0x1
+#define POLARIS10_THERMAL_LOW_ALERT_MASK          0x2
 
-#define ELLESMERE_THERMAL_MINIMUM_TEMP_READING    -256
-#define ELLESMERE_THERMAL_MAXIMUM_TEMP_READING    255
+#define POLARIS10_THERMAL_MINIMUM_TEMP_READING    -256
+#define POLARIS10_THERMAL_MAXIMUM_TEMP_READING    255
 
-#define ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP      0
-#define ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP      255
+#define POLARIS10_THERMAL_MINIMUM_ALERT_TEMP      0
+#define POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP      255
 
 #define FDO_PWM_MODE_STATIC  1
 #define FDO_PWM_MODE_STATIC_RPM 5
 
 
-extern int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-extern int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-extern int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
-
-extern int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr);
-extern int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
-extern int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
-extern int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
-extern int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
-extern int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
-extern int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
-extern int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
-extern int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr);
-extern int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
-extern int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
-extern int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
-extern int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
+extern int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
+extern int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
+extern int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result);
+
+extern int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
+extern int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
+extern int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
+extern int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
+extern int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
+extern int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
+extern int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
+extern int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
+extern int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr);
+extern int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
+extern int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
+extern int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
+extern int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
 extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr);
 
 #endif

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h

@@ -209,18 +209,18 @@ typedef struct _ATOM_Tonga_PCIE_Table {
 	ATOM_Tonga_PCIE_Record entries[1];							/* Dynamically allocate entries. */
 } ATOM_Tonga_PCIE_Table;
 
-typedef struct _ATOM_Ellesmere_PCIE_Record {
+typedef struct _ATOM_Polaris10_PCIE_Record {
 	UCHAR ucPCIEGenSpeed;
 	UCHAR usPCIELaneWidth;
 	UCHAR ucReserved[2];
 	ULONG ulPCIE_Sclk;
-} ATOM_Ellesmere_PCIE_Record;
+} ATOM_Polaris10_PCIE_Record;
 
-typedef struct _ATOM_Ellesmere_PCIE_Table {
+typedef struct _ATOM_Polaris10_PCIE_Table {
 	UCHAR ucRevId;
 	UCHAR ucNumEntries;                                         /* Number of entries. */
-	ATOM_Ellesmere_PCIE_Record entries[1];                      /* Dynamically allocate entries. */
-} ATOM_Ellesmere_PCIE_Table;
+	ATOM_Polaris10_PCIE_Record entries[1];                      /* Dynamically allocate entries. */
+} ATOM_Polaris10_PCIE_Table;
 
 
 typedef struct _ATOM_Tonga_MM_Dependency_Record {

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c

@@ -493,8 +493,8 @@ static int get_pcie_table(
 
 		*pp_tonga_pcie_table = pcie_table;
 	} else {
-		/* Ellesmere/Baffin and newer. */
-		const ATOM_Ellesmere_PCIE_Table *atom_pcie_table = (ATOM_Ellesmere_PCIE_Table *)pTable;
+		/* Polaris10/Polaris11 and newer. */
+		const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable;
 		PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0),
 			"Invalid PowerPlay Table!", return -1);
 

drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h → drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h

@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef ELLESMERE_PP_SMC_H
-#define ELLESMERE_PP_SMC_H
+#ifndef POLARIS10_PP_SMC_H
+#define POLARIS10_PP_SMC_H
 
 
 #pragma pack(push, 1)
@@ -386,8 +386,16 @@ typedef uint16_t PPSMC_Result;
 
 #define PPSMC_MSG_GFX_CU_PG_ENABLE            ((uint16_t) 0x280)
 #define PPSMC_MSG_GFX_CU_PG_DISABLE           ((uint16_t) 0x281)
+#define PPSMC_MSG_GetCurrPkgPwr               ((uint16_t) 0x282)
 
 #define PPSMC_MSG_SetGpuPllDfsForSclk         ((uint16_t) 0x300)
+#define PPSMC_MSG_Didt_Block_Function		  ((uint16_t) 0x301)
+
+#define PPSMC_MSG_SecureSRBMWrite             ((uint16_t) 0x600)
+#define PPSMC_MSG_SecureSRBMRead              ((uint16_t) 0x601)
+#define PPSMC_MSG_SetAddress                  ((uint16_t) 0x800)
+#define PPSMC_MSG_GetData                     ((uint16_t) 0x801)
+#define PPSMC_MSG_SetData                     ((uint16_t) 0x802)
 
 typedef uint16_t PPSMC_Msg;
 

drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h → drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h

@@ -20,8 +20,8 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  */
-#ifndef _ELLESMERE_PWRVIRUS_H
-#define _ELLESMERE_PWRVIRUS_H
+#ifndef _POLARIS10_PWRVIRUS_H
+#define _POLARIS10_PWRVIRUS_H
 
 #define mmSMC_IND_INDEX_11                              0x01AC
 #define mmSMC_IND_DATA_11                               0x01AD

drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h

@@ -705,6 +705,7 @@ struct SMU7_Discrete_Pm_Status_Table {
 	uint16_t Sclk_dpm_residency[8];
 	uint16_t Uvd_dpm_residency[8];
 	uint16_t Vce_dpm_residency[8];
+	uint16_t Mclk_dpm_residency[4];
 
 	uint32_t P_vddci_acc;
 	uint32_t P_vddr1_acc;
@@ -779,6 +780,47 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
 
+// DIDT Defines
+#define SQ_Enable_MASK 0x1
+#define SQ_IR_MASK 0x2
+#define SQ_PCC_MASK 0x4
+#define SQ_EDC_MASK 0x8
+
+#define TCP_Enable_MASK 0x100
+#define TCP_IR_MASK 0x200
+#define TCP_PCC_MASK 0x400
+#define TCP_EDC_MASK 0x800
+
+#define TD_Enable_MASK 0x10000
+#define TD_IR_MASK 0x20000
+#define TD_PCC_MASK 0x40000
+#define TD_EDC_MASK 0x80000
+
+#define DB_Enable_MASK 0x1000000
+#define DB_IR_MASK 0x2000000
+#define DB_PCC_MASK 0x4000000 
+#define DB_EDC_MASK 0x8000000
+
+#define SQ_Enable_SHIFT 0
+#define SQ_IR_SHIFT 1
+#define SQ_PCC_SHIFT 2
+#define SQ_EDC_SHIFT 3
+
+#define TCP_Enable_SHIFT 8
+#define TCP_IR_SHIFT 9
+#define TCP_PCC_SHIFT 10
+#define TCP_EDC_SHIFT 11
+
+#define TD_Enable_SHIFT 16
+#define TD_IR_SHIFT 17
+#define TD_PCC_SHIFT 18
+#define TD_EDC_SHIFT 19
+
+#define DB_Enable_SHIFT 24
+#define DB_IR_SHIFT 25
+#define DB_PCC_SHIFT 26 
+#define DB_EDC_SHIFT 27
+
 #pragma pack(pop)
 
 

drivers/gpu/drm/amd/powerplay/smumgr/Makefile

@@ -2,7 +2,7 @@
 # Makefile for the 'smu manager' sub-component of powerplay.
 # It provides the smu management services for the driver.
 
-SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o
+SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o polaris10_smumgr.o
 
 AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR))
 

drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h → drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h

@@ -21,18 +21,18 @@
  *
  */
 
-#ifndef _ELLESMERE_SMUMANAGER_H
-#define _ELLESMERE_SMUMANAGER_H
+#ifndef _POLARIS10_SMUMANAGER_H
+#define _POLARIS10_SMUMANAGER_H
 
-#include <ellesmere_ppsmc.h>
+#include <polaris10_ppsmc.h>
 #include <pp_endian.h>
 
-struct ellesmere_avfs {
+struct polaris10_avfs {
 	enum AVFS_BTC_STATUS avfs_btc_status;
 	uint32_t           avfs_btc_param;
 };
 
-struct ellesmere_buffer_entry {
+struct polaris10_buffer_entry {
 	uint32_t data_size;
 	uint32_t mc_addr_low;
 	uint32_t mc_addr_high;
@@ -40,11 +40,11 @@ struct ellesmere_buffer_entry {
 	unsigned long  handle;
 };
 
-struct ellesmere_smumgr {
+struct polaris10_smumgr {
 	uint8_t *header;
 	uint8_t *mec_image;
-	struct ellesmere_buffer_entry smu_buffer;
-	struct ellesmere_buffer_entry header_buffer;
+	struct polaris10_buffer_entry smu_buffer;
+	struct polaris10_buffer_entry header_buffer;
 	uint32_t soft_regs_start;
 	uint8_t *read_rrm_straps;
 	uint32_t read_drm_straps_mc_address_high;
@@ -53,15 +53,15 @@ struct ellesmere_smumgr {
 	bool post_initial_boot;
 	uint8_t protected_mode;
 	uint8_t security_hard_key;
-	struct ellesmere_avfs  avfs;
+	struct polaris10_avfs  avfs;
 };
 
 
-int ellesmere_smum_init(struct pp_smumgr *smumgr);
+int polaris10_smum_init(struct pp_smumgr *smumgr);
 
-int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
-int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
-int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
+int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit);
+int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit);
+int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address,
 				const uint8_t *src, uint32_t byte_count, uint32_t limit);
 
 #endif