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kernel_linux
提交 213a8434 编写于 作者: A Alan Cox 提交者： Dave Airlie
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gma500: use the register map to clean up 

Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>
上级 8512e074
展开全部 隐藏空白更改
内联 并排
Showing with 473 addition and 783 deletion
drivers/gpu/drm/gma500/cdv_device.c
浏览文件 @ 213a8434
...@@ -494,6 +494,7 @@ static const struct psb_offset cdv_regmap[2] = { ...@@ -494,6 +494,7 @@ static const struct psb_offset cdv_regmap[2] = {
.conf = PIPEACONF, .conf = PIPEACONF,
.src = PIPEASRC, .src = PIPEASRC,
.dpll = DPLL_A, .dpll = DPLL_A,
.dpll_md = DPLL_A_MD,
.htotal = HTOTAL_A, .htotal = HTOTAL_A,
.hblank = HBLANK_A, .hblank = HBLANK_A,
.hsync = HSYNC_A, .hsync = HSYNC_A,
...@@ -518,6 +519,7 @@ static const struct psb_offset cdv_regmap[2] = { ...@@ -518,6 +519,7 @@ static const struct psb_offset cdv_regmap[2] = {
.conf = PIPEBCONF, .conf = PIPEBCONF,
.src = PIPEBSRC, .src = PIPEBSRC,
.dpll = DPLL_B, .dpll = DPLL_B,
.dpll_md = DPLL_B_MD,
.htotal = HTOTAL_B, .htotal = HTOTAL_B,
.hblank = HBLANK_B, .hblank = HBLANK_B,
.hsync = HSYNC_B, .hsync = HSYNC_B,
......
drivers/gpu/drm/gma500/mdfld_device.c
浏览文件 @ 213a8434
...@@ -168,30 +168,12 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum) ...@@ -168,30 +168,12 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct medfield_state *regs = &dev_priv->regs.mdfld; struct medfield_state *regs = &dev_priv->regs.mdfld;
struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum]; struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
const struct psb_offset *map = &dev_priv->regmap[pipenum];
int i; int i;
u32 *mipi_val; u32 *mipi_val;
/* register */ /* register */
u32 dpll_reg = MRST_DPLL_A;
u32 fp_reg = MRST_FPA0;
u32 pipeconf_reg = PIPEACONF;
u32 htot_reg = HTOTAL_A;
u32 hblank_reg = HBLANK_A;
u32 hsync_reg = HSYNC_A;
u32 vtot_reg = VTOTAL_A;
u32 vblank_reg = VBLANK_A;
u32 vsync_reg = VSYNC_A;
u32 pipesrc_reg = PIPEASRC;
u32 dspstride_reg = DSPASTRIDE;
u32 dsplinoff_reg = DSPALINOFF;
u32 dsptileoff_reg = DSPATILEOFF;
u32 dspsize_reg = DSPASIZE;
u32 dsppos_reg = DSPAPOS;
u32 dspsurf_reg = DSPASURF;
u32 mipi_reg = MIPI; u32 mipi_reg = MIPI;
u32 dspcntr_reg = DSPACNTR;
u32 dspstatus_reg = PIPEASTAT;
u32 palette_reg = PALETTE_A;
switch (pipenum) { switch (pipenum) {
case 0: case 0:
...@@ -199,48 +181,10 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum) ...@@ -199,48 +181,10 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
break; break;
case 1: case 1:
mipi_val = &regs->saveMIPI; mipi_val = &regs->saveMIPI;
/* register */
dpll_reg = MDFLD_DPLL_B;
fp_reg = MDFLD_DPLL_DIV0;
pipeconf_reg = PIPEBCONF;
htot_reg = HTOTAL_B;
hblank_reg = HBLANK_B;
hsync_reg = HSYNC_B;
vtot_reg = VTOTAL_B;
vblank_reg = VBLANK_B;
vsync_reg = VSYNC_B;
pipesrc_reg = PIPEBSRC;
dspstride_reg = DSPBSTRIDE;
dsplinoff_reg = DSPBLINOFF;
dsptileoff_reg = DSPBTILEOFF;
dspsize_reg = DSPBSIZE;
dsppos_reg = DSPBPOS;
dspsurf_reg = DSPBSURF;
dspcntr_reg = DSPBCNTR;
dspstatus_reg = PIPEBSTAT;
palette_reg = PALETTE_B;
break; break;
case 2: case 2:
/* register */ /* register */
pipeconf_reg = PIPECCONF;
htot_reg = HTOTAL_C;
hblank_reg = HBLANK_C;
hsync_reg = HSYNC_C;
vtot_reg = VTOTAL_C;
vblank_reg = VBLANK_C;
vsync_reg = VSYNC_C;
pipesrc_reg = PIPECSRC;
dspstride_reg = DSPCSTRIDE;
dsplinoff_reg = DSPCLINOFF;
dsptileoff_reg = DSPCTILEOFF;
dspsize_reg = DSPCSIZE;
dsppos_reg = DSPCPOS;
dspsurf_reg = DSPCSURF;
mipi_reg = MIPI_C; mipi_reg = MIPI_C;
dspcntr_reg = DSPCCNTR;
dspstatus_reg = PIPECSTAT;
palette_reg = PALETTE_C;
/* pointer to values */ /* pointer to values */
mipi_val = &regs->saveMIPI_C; mipi_val = &regs->saveMIPI_C;
break; break;
...@@ -250,28 +194,28 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum) ...@@ -250,28 +194,28 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
} }
/* Pipe & plane A info */ /* Pipe & plane A info */
pipe->dpll = PSB_RVDC32(dpll_reg); pipe->dpll = PSB_RVDC32(map->dpll);
pipe->fp0 = PSB_RVDC32(fp_reg); pipe->fp0 = PSB_RVDC32(map->fp0);
pipe->conf = PSB_RVDC32(pipeconf_reg); pipe->conf = PSB_RVDC32(map->conf);
pipe->htotal = PSB_RVDC32(htot_reg); pipe->htotal = PSB_RVDC32(map->htotal);
pipe->hblank = PSB_RVDC32(hblank_reg); pipe->hblank = PSB_RVDC32(map->hblank);
pipe->hsync = PSB_RVDC32(hsync_reg); pipe->hsync = PSB_RVDC32(map->hsync);
pipe->vtotal = PSB_RVDC32(vtot_reg); pipe->vtotal = PSB_RVDC32(map->vtotal);
pipe->vblank = PSB_RVDC32(vblank_reg); pipe->vblank = PSB_RVDC32(map->vblank);
pipe->vsync = PSB_RVDC32(vsync_reg); pipe->vsync = PSB_RVDC32(map->vsync);
pipe->src = PSB_RVDC32(pipesrc_reg); pipe->src = PSB_RVDC32(map->src);
pipe->stride = PSB_RVDC32(dspstride_reg); pipe->stride = PSB_RVDC32(map->stride);
pipe->linoff = PSB_RVDC32(dsplinoff_reg); pipe->linoff = PSB_RVDC32(map->linoff);
pipe->tileoff = PSB_RVDC32(dsptileoff_reg); pipe->tileoff = PSB_RVDC32(map->tileoff);
pipe->size = PSB_RVDC32(dspsize_reg); pipe->size = PSB_RVDC32(map->size);
pipe->pos = PSB_RVDC32(dsppos_reg); pipe->pos = PSB_RVDC32(map->pos);
pipe->surf = PSB_RVDC32(dspsurf_reg); pipe->surf = PSB_RVDC32(map->surf);
pipe->cntr = PSB_RVDC32(dspcntr_reg); pipe->cntr = PSB_RVDC32(map->cntr);
pipe->status = PSB_RVDC32(dspstatus_reg); pipe->status = PSB_RVDC32(map->status);
/*save palette (gamma) */ /*save palette (gamma) */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
pipe->palette[i] = PSB_RVDC32(palette_reg + (i << 2)); pipe->palette[i] = PSB_RVDC32(map->palette + (i << 2));
if (pipenum == 1) { if (pipenum == 1) {
regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
...@@ -302,31 +246,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -302,31 +246,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
struct mdfld_dsi_config *dsi_config = NULL; struct mdfld_dsi_config *dsi_config = NULL;
struct medfield_state *regs = &dev_priv->regs.mdfld; struct medfield_state *regs = &dev_priv->regs.mdfld;
struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum]; struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
const struct psb_offset *map = &dev_priv->regmap[pipenum];
u32 i; u32 i;
u32 dpll; u32 dpll;
u32 timeout = 0; u32 timeout = 0;
/* register */ /* register */
u32 dpll_reg = MRST_DPLL_A;
u32 fp_reg = MRST_FPA0;
u32 pipeconf_reg = PIPEACONF;
u32 htot_reg = HTOTAL_A;
u32 hblank_reg = HBLANK_A;
u32 hsync_reg = HSYNC_A;
u32 vtot_reg = VTOTAL_A;
u32 vblank_reg = VBLANK_A;
u32 vsync_reg = VSYNC_A;
u32 pipesrc_reg = PIPEASRC;
u32 dspstride_reg = DSPASTRIDE;
u32 dsplinoff_reg = DSPALINOFF;
u32 dsptileoff_reg = DSPATILEOFF;
u32 dspsize_reg = DSPASIZE;
u32 dsppos_reg = DSPAPOS;
u32 dspsurf_reg = DSPASURF;
u32 dspstatus_reg = PIPEASTAT;
u32 mipi_reg = MIPI; u32 mipi_reg = MIPI;
u32 dspcntr_reg = DSPACNTR;
u32 palette_reg = PALETTE_A;
/* values */ /* values */
u32 dpll_val = pipe->dpll; u32 dpll_val = pipe->dpll;
...@@ -338,52 +264,10 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -338,52 +264,10 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
dsi_config = dev_priv->dsi_configs[0]; dsi_config = dev_priv->dsi_configs[0];
break; break;
case 1: case 1:
/* register */
dpll_reg = MDFLD_DPLL_B;
fp_reg = MDFLD_DPLL_DIV0;
pipeconf_reg = PIPEBCONF;
htot_reg = HTOTAL_B;
hblank_reg = HBLANK_B;
hsync_reg = HSYNC_B;
vtot_reg = VTOTAL_B;
vblank_reg = VBLANK_B;
vsync_reg = VSYNC_B;
pipesrc_reg = PIPEBSRC;
dspstride_reg = DSPBSTRIDE;
dsplinoff_reg = DSPBLINOFF;
dsptileoff_reg = DSPBTILEOFF;
dspsize_reg = DSPBSIZE;
dsppos_reg = DSPBPOS;
dspsurf_reg = DSPBSURF;
dspcntr_reg = DSPBCNTR;
dspstatus_reg = PIPEBSTAT;
palette_reg = PALETTE_B;
/* values */
dpll_val &= ~DPLL_VCO_ENABLE; dpll_val &= ~DPLL_VCO_ENABLE;
break; break;
case 2: case 2:
/* register */
pipeconf_reg = PIPECCONF;
htot_reg = HTOTAL_C;
hblank_reg = HBLANK_C;
hsync_reg = HSYNC_C;
vtot_reg = VTOTAL_C;
vblank_reg = VBLANK_C;
vsync_reg = VSYNC_C;
pipesrc_reg = PIPECSRC;
dspstride_reg = DSPCSTRIDE;
dsplinoff_reg = DSPCLINOFF;
dsptileoff_reg = DSPCTILEOFF;
dspsize_reg = DSPCSIZE;
dsppos_reg = DSPCPOS;
dspsurf_reg = DSPCSURF;
mipi_reg = MIPI_C; mipi_reg = MIPI_C;
dspcntr_reg = DSPCCNTR;
dspstatus_reg = PIPECSTAT;
palette_reg = PALETTE_C;
/* values */
mipi_val = regs->saveMIPI_C; mipi_val = regs->saveMIPI_C;
dsi_config = dev_priv->dsi_configs[1]; dsi_config = dev_priv->dsi_configs[1];
break; break;
...@@ -396,13 +280,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -396,13 +280,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
PSB_WVDC32(0x80000000, VGACNTRL); PSB_WVDC32(0x80000000, VGACNTRL);
if (pipenum == 1) { if (pipenum == 1) {
PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg); PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll);
PSB_RVDC32(dpll_reg); PSB_RVDC32(map->dpll);
PSB_WVDC32(pipe->fp0, fp_reg); PSB_WVDC32(pipe->fp0, map->fp0);
} else { } else {
dpll = PSB_RVDC32(dpll_reg); dpll = PSB_RVDC32(map->dpll);
if (!(dpll & DPLL_VCO_ENABLE)) { if (!(dpll & DPLL_VCO_ENABLE)) {
...@@ -410,23 +294,23 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -410,23 +294,23 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
before enable the VCO */ before enable the VCO */
if (dpll & MDFLD_PWR_GATE_EN) { if (dpll & MDFLD_PWR_GATE_EN) {
dpll &= ~MDFLD_PWR_GATE_EN; dpll &= ~MDFLD_PWR_GATE_EN;
PSB_WVDC32(dpll, dpll_reg); PSB_WVDC32(dpll, map->dpll);
/* FIXME_MDFLD PO - change 500 to 1 after PO */ /* FIXME_MDFLD PO - change 500 to 1 after PO */
udelay(500); udelay(500);
} }
PSB_WVDC32(pipe->fp0, fp_reg); PSB_WVDC32(pipe->fp0, map->fp0);
PSB_WVDC32(dpll_val, dpll_reg); PSB_WVDC32(dpll_val, map->dpll);
/* FIXME_MDFLD PO - change 500 to 1 after PO */ /* FIXME_MDFLD PO - change 500 to 1 after PO */
udelay(500); udelay(500);
dpll_val |= DPLL_VCO_ENABLE; dpll_val |= DPLL_VCO_ENABLE;
PSB_WVDC32(dpll_val, dpll_reg); PSB_WVDC32(dpll_val, map->dpll);
PSB_RVDC32(dpll_reg); PSB_RVDC32(map->dpll);
/* wait for DSI PLL to lock */ /* wait for DSI PLL to lock */
while (timeout < 20000 && while (timeout < 20000 &&
!(PSB_RVDC32(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) { !(PSB_RVDC32(map->conf) & PIPECONF_DSIPLL_LOCK)) {
udelay(150); udelay(150);
timeout++; timeout++;
} }
...@@ -439,28 +323,28 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -439,28 +323,28 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
} }
} }
/* Restore mode */ /* Restore mode */
PSB_WVDC32(pipe->htotal, htot_reg); PSB_WVDC32(pipe->htotal, map->htotal);
PSB_WVDC32(pipe->hblank, hblank_reg); PSB_WVDC32(pipe->hblank, map->hblank);
PSB_WVDC32(pipe->hsync, hsync_reg); PSB_WVDC32(pipe->hsync, map->hsync);
PSB_WVDC32(pipe->vtotal, vtot_reg); PSB_WVDC32(pipe->vtotal, map->vtotal);
PSB_WVDC32(pipe->vblank, vblank_reg); PSB_WVDC32(pipe->vblank, map->vblank);
PSB_WVDC32(pipe->vsync, vsync_reg); PSB_WVDC32(pipe->vsync, map->vsync);
PSB_WVDC32(pipe->src, pipesrc_reg); PSB_WVDC32(pipe->src, map->src);
PSB_WVDC32(pipe->status, dspstatus_reg); PSB_WVDC32(pipe->status, map->status);
/*set up the plane*/ /*set up the plane*/
PSB_WVDC32(pipe->stride, dspstride_reg); PSB_WVDC32(pipe->stride, map->stride);
PSB_WVDC32(pipe->linoff, dsplinoff_reg); PSB_WVDC32(pipe->linoff, map->linoff);
PSB_WVDC32(pipe->tileoff, dsptileoff_reg); PSB_WVDC32(pipe->tileoff, map->tileoff);
PSB_WVDC32(pipe->size, dspsize_reg); PSB_WVDC32(pipe->size, map->size);
PSB_WVDC32(pipe->pos, dsppos_reg); PSB_WVDC32(pipe->pos, map->pos);
PSB_WVDC32(pipe->surf, dspsurf_reg); PSB_WVDC32(pipe->surf, map->surf);
if (pipenum == 1) { if (pipenum == 1) {
/* restore palette (gamma) */ /* restore palette (gamma) */
/*DRM_UDELAY(50000); */ /*DRM_UDELAY(50000); */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
PSB_WVDC32(pipe->palette[i], palette_reg + (i << 2)); PSB_WVDC32(pipe->palette[i], map->palette + (i << 2));
PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL); PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL);
PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
...@@ -470,7 +354,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -470,7 +354,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
/*TODO: resume pipe*/ /*TODO: resume pipe*/
/*enable the plane*/ /*enable the plane*/
PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, dspcntr_reg); PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr);
return 0; return 0;
} }
...@@ -488,7 +372,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -488,7 +372,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
msleep(20); msleep(20);
/*enable the plane*/ /*enable the plane*/
PSB_WVDC32(pipe->cntr, dspcntr_reg); PSB_WVDC32(pipe->cntr, map->cntr);
if (in_atomic() || in_interrupt()) if (in_atomic() || in_interrupt())
mdelay(20); mdelay(20);
...@@ -517,12 +401,12 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum) ...@@ -517,12 +401,12 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
mdelay(1); mdelay(1);
/*enable the pipe*/ /*enable the pipe*/
PSB_WVDC32(pipe->conf, pipeconf_reg); PSB_WVDC32(pipe->conf, map->conf);
/* restore palette (gamma) */ /* restore palette (gamma) */
/*DRM_UDELAY(50000); */ /*DRM_UDELAY(50000); */
for (i = 0; i < 256; i++) for (i = 0; i < 256; i++)
PSB_WVDC32(pipe->palette[i], palette_reg + (i << 2)); PSB_WVDC32(pipe->palette[i], map->palette + (i << 2));
return 0; return 0;
} }
...@@ -578,7 +462,7 @@ static const struct psb_offset mdfld_regmap[3] = { ...@@ -578,7 +462,7 @@ static const struct psb_offset mdfld_regmap[3] = {
.size = DSPASIZE, .size = DSPASIZE,
.pos = DSPAPOS, .pos = DSPAPOS,
.surf = DSPASURF, .surf = DSPASURF,
.addr = DSPABASE, .addr = MRST_DSPABASE,
.status = PIPEASTAT, .status = PIPEASTAT,
.linoff = DSPALINOFF, .linoff = DSPALINOFF,
.tileoff = DSPATILEOFF, .tileoff = DSPATILEOFF,
...@@ -600,13 +484,14 @@ static const struct psb_offset mdfld_regmap[3] = { ...@@ -600,13 +484,14 @@ static const struct psb_offset mdfld_regmap[3] = {
.size = DSPBSIZE, .size = DSPBSIZE,
.pos = DSPBPOS, .pos = DSPBPOS,
.surf = DSPBSURF, .surf = DSPBSURF,
.addr = DSPBBASE, .addr = MRST_DSPBBASE,
.status = PIPEBSTAT, .status = PIPEBSTAT,
.linoff = DSPBLINOFF, .linoff = DSPBLINOFF,
.tileoff = DSPBTILEOFF, .tileoff = DSPBTILEOFF,
.palette = PALETTE_B, .palette = PALETTE_B,
}, },
{ {
.fp0 = MRST_FPA0, /* This is what the old code did ?? */
.cntr = DSPCCNTR, .cntr = DSPCCNTR,
.conf = PIPECCONF, .conf = PIPECCONF,
.src = PIPECSRC, .src = PIPECSRC,
...@@ -622,7 +507,7 @@ static const struct psb_offset mdfld_regmap[3] = { ...@@ -622,7 +507,7 @@ static const struct psb_offset mdfld_regmap[3] = {
.size = DSPBSIZE, .size = DSPBSIZE,
.pos = DSPCPOS, .pos = DSPCPOS,
.surf = DSPCSURF, .surf = DSPCSURF,
.addr = DSPCBASE, .addr = MDFLD_DSPCBASE,
.status = PIPECSTAT, .status = PIPECSTAT,
.linoff = DSPCLINOFF, .linoff = DSPCLINOFF,
.tileoff = DSPCTILEOFF, .tileoff = DSPCTILEOFF,
......
drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c
浏览文件 @ 213a8434
...@@ -605,6 +605,8 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector, ...@@ -605,6 +605,8 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
struct mdfld_dsi_config *dsi_config = struct mdfld_dsi_config *dsi_config =
mdfld_dsi_get_config(dsi_connector); mdfld_dsi_get_config(dsi_connector);
struct drm_device *dev = dsi_config->dev; struct drm_device *dev = dsi_config->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
const struct psb_offset *map = &dev_priv->regmap[pipe];
u32 mipi_val = 0; u32 mipi_val = 0;
if (!dsi_connector) { if (!dsi_connector) {
...@@ -632,21 +634,13 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector, ...@@ -632,21 +634,13 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
pkg_sender->status = MDFLD_DSI_PKG_SENDER_FREE; pkg_sender->status = MDFLD_DSI_PKG_SENDER_FREE;
/*init regs*/ /*init regs*/
if (pipe == 0) { /* FIXME: should just copy the regmap ptr ? */
pkg_sender->dpll_reg = MRST_DPLL_A; pkg_sender->dpll_reg = map->dpll;
pkg_sender->dspcntr_reg = DSPACNTR; pkg_sender->dspcntr_reg = map->cntr;
pkg_sender->pipeconf_reg = PIPEACONF; pkg_sender->pipeconf_reg = map->conf;
pkg_sender->dsplinoff_reg = DSPALINOFF; pkg_sender->dsplinoff_reg = map->linoff;
pkg_sender->dspsurf_reg = DSPASURF; pkg_sender->dspsurf_reg = map->surf;
pkg_sender->pipestat_reg = PIPEASTAT; pkg_sender->pipestat_reg = map->status;
} else if (pipe == 2) {
pkg_sender->dpll_reg = MRST_DPLL_A;
pkg_sender->dspcntr_reg = DSPCCNTR;
pkg_sender->pipeconf_reg = PIPECCONF;
pkg_sender->dsplinoff_reg = DSPCLINOFF;
pkg_sender->dspsurf_reg = DSPCSURF;
pkg_sender->pipestat_reg = PIPECSTAT;
}
pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe); pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe);
pkg_sender->mipi_lp_gen_data_reg = MIPI_LP_GEN_DATA_REG(pipe); pkg_sender->mipi_lp_gen_data_reg = MIPI_LP_GEN_DATA_REG(pipe);
......
drivers/gpu/drm/gma500/oaktrail_crtc.c
浏览文件 @ 213a8434
...@@ -162,12 +162,10 @@ mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk, ...@@ -162,12 +162,10 @@ mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B; const struct psb_offset *map = &dev_priv->regmap[pipe];
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
int dspbase_reg = (pipe == 0) ? MRST_DSPABASE : DSPBBASE;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
u32 temp; u32 temp;
if (!gma_power_begin(dev, true)) if (!gma_power_begin(dev, true))
...@@ -181,32 +179,32 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) ...@@ -181,32 +179,32 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_SUSPEND:
/* Enable the DPLL */ /* Enable the DPLL */
temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll);
if ((temp & DPLL_VCO_ENABLE) == 0) { if ((temp & DPLL_VCO_ENABLE) == 0) {
REG_WRITE(dpll_reg, temp); REG_WRITE(map->dpll, temp);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
} }
/* Enable the pipe */ /* Enable the pipe */
temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf);
if ((temp & PIPEACONF_ENABLE) == 0) if ((temp & PIPEACONF_ENABLE) == 0)
REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
/* Enable the plane */ /* Enable the plane */
temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr);
if ((temp & DISPLAY_PLANE_ENABLE) == 0) { if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr,
temp | DISPLAY_PLANE_ENABLE); temp | DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */ /* Flush the plane changes */
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_WRITE(map->base, REG_READ(map->base));
} }
psb_intel_crtc_load_lut(crtc); psb_intel_crtc_load_lut(crtc);
...@@ -223,28 +221,28 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) ...@@ -223,28 +221,28 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
/* Disable the VGA plane that we never use */ /* Disable the VGA plane that we never use */
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
/* Disable display plane */ /* Disable display plane */
temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr);
if ((temp & DISPLAY_PLANE_ENABLE) != 0) { if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr,
temp & ~DISPLAY_PLANE_ENABLE); temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */ /* Flush the plane changes */
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_WRITE(map->base, REG_READ(map->base));
REG_READ(dspbase_reg); REG_READ(map->base);
} }
/* Next, disable display pipes */ /* Next, disable display pipes */
temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf);
if ((temp & PIPEACONF_ENABLE) != 0) { if ((temp & PIPEACONF_ENABLE) != 0) {
REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
REG_READ(pipeconf_reg); REG_READ(map->conf);
} }
/* Wait for for the pipe disable to take effect. */ /* Wait for for the pipe disable to take effect. */
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll);
if ((temp & DPLL_VCO_ENABLE) != 0) { if ((temp & DPLL_VCO_ENABLE) != 0) {
REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
} }
/* Wait for the clocks to turn off. */ /* Wait for the clocks to turn off. */
...@@ -292,17 +290,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, ...@@ -292,17 +290,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0; const struct psb_offset *map = &dev_priv->regmap[pipe];
int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
int refclk = 0; int refclk = 0;
struct oaktrail_clock_t clock; struct oaktrail_clock_t clock;
u32 dpll = 0, fp = 0, dspcntr, pipeconf; u32 dpll = 0, fp = 0, dspcntr, pipeconf;
...@@ -350,7 +338,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, ...@@ -350,7 +338,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
if (oaktrail_panel_fitter_pipe(dev) == pipe) if (oaktrail_panel_fitter_pipe(dev) == pipe)
REG_WRITE(PFIT_CONTROL, 0); REG_WRITE(PFIT_CONTROL, 0);
REG_WRITE(pipesrc_reg, REG_WRITE(map->src,
((mode->crtc_hdisplay - 1) << 16) | ((mode->crtc_hdisplay - 1) << 16) |
(mode->crtc_vdisplay - 1)); (mode->crtc_vdisplay - 1));
...@@ -369,34 +357,34 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, ...@@ -369,34 +357,34 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
offsetY = (adjusted_mode->crtc_vdisplay - offsetY = (adjusted_mode->crtc_vdisplay -
mode->crtc_vdisplay) / 2; mode->crtc_vdisplay) / 2;
REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) | REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
((adjusted_mode->crtc_htotal - 1) << 16)); ((adjusted_mode->crtc_htotal - 1) << 16));
REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) | REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
((adjusted_mode->crtc_vtotal - 1) << 16)); ((adjusted_mode->crtc_vtotal - 1) << 16));
REG_WRITE(hblank_reg, REG_WRITE(map->hblank,
(adjusted_mode->crtc_hblank_start - offsetX - 1) | (adjusted_mode->crtc_hblank_start - offsetX - 1) |
((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16)); ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
REG_WRITE(hsync_reg, REG_WRITE(map->hsync,
(adjusted_mode->crtc_hsync_start - offsetX - 1) | (adjusted_mode->crtc_hsync_start - offsetX - 1) |
((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16)); ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
REG_WRITE(vblank_reg, REG_WRITE(map->vblank,
(adjusted_mode->crtc_vblank_start - offsetY - 1) | (adjusted_mode->crtc_vblank_start - offsetY - 1) |
((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16)); ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
REG_WRITE(vsync_reg, REG_WRITE(map->vsync,
(adjusted_mode->crtc_vsync_start - offsetY - 1) | (adjusted_mode->crtc_vsync_start - offsetY - 1) |
((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16)); ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
} else { } else {
REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
((adjusted_mode->crtc_htotal - 1) << 16)); ((adjusted_mode->crtc_htotal - 1) << 16));
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
((adjusted_mode->crtc_vtotal - 1) << 16)); ((adjusted_mode->crtc_vtotal - 1) << 16));
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
((adjusted_mode->crtc_hblank_end - 1) << 16)); ((adjusted_mode->crtc_hblank_end - 1) << 16));
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
((adjusted_mode->crtc_hsync_end - 1) << 16)); ((adjusted_mode->crtc_hsync_end - 1) << 16));
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
((adjusted_mode->crtc_vblank_end - 1) << 16)); ((adjusted_mode->crtc_vblank_end - 1) << 16));
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16)); ((adjusted_mode->crtc_vsync_end - 1) << 16));
} }
...@@ -408,10 +396,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, ...@@ -408,10 +396,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
} }
/* setup pipeconf */ /* setup pipeconf */
pipeconf = REG_READ(pipeconf_reg); pipeconf = REG_READ(map->conf);
/* Set up the display plane register */ /* Set up the display plane register */
dspcntr = REG_READ(dspcntr_reg); dspcntr = REG_READ(map->cntr);
dspcntr |= DISPPLANE_GAMMA_ENABLE; dspcntr |= DISPPLANE_GAMMA_ENABLE;
if (pipe == 0) if (pipe == 0)
...@@ -467,30 +455,30 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, ...@@ -467,30 +455,30 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
mrstPrintPll("chosen", &clock); mrstPrintPll("chosen", &clock);
if (dpll & DPLL_VCO_ENABLE) { if (dpll & DPLL_VCO_ENABLE) {
REG_WRITE(fp_reg, fp); REG_WRITE(map->fp0, fp);
REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Check the DPLLA lock bit PIPEACONF[29] */ /* Check the DPLLA lock bit PIPEACONF[29] */
udelay(150); udelay(150);
} }
REG_WRITE(fp_reg, fp); REG_WRITE(map->fp0, fp);
REG_WRITE(dpll_reg, dpll); REG_WRITE(map->dpll, dpll);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
/* write it again -- the BIOS does, after all */ /* write it again -- the BIOS does, after all */
REG_WRITE(dpll_reg, dpll); REG_WRITE(map->dpll, dpll);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
REG_WRITE(pipeconf_reg, pipeconf); REG_WRITE(map->conf, pipeconf);
REG_READ(pipeconf_reg); REG_READ(map->conf);
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr);
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
oaktrail_crtc_mode_set_exit: oaktrail_crtc_mode_set_exit:
...@@ -509,15 +497,13 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc, ...@@ -509,15 +497,13 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
int x, int y, struct drm_framebuffer *old_fb) int x, int y, struct drm_framebuffer *old_fb)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
const struct psb_offset *map = &dev_priv->regmap[pipe];
unsigned long start, offset; unsigned long start, offset;
int dspbase = (pipe == 0 ? DSPALINOFF : DSPBBASE);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
u32 dspcntr; u32 dspcntr;
int ret = 0; int ret = 0;
...@@ -533,9 +519,9 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc, ...@@ -533,9 +519,9 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
start = psbfb->gtt->offset; start = psbfb->gtt->offset;
offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
REG_WRITE(dspstride, crtc->fb->pitches[0]); REG_WRITE(map->stride, crtc->fb->pitches[0]);
dspcntr = REG_READ(dspcntr_reg); dspcntr = REG_READ(map->cntr);
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
switch (crtc->fb->bits_per_pixel) { switch (crtc->fb->bits_per_pixel) {
...@@ -557,12 +543,12 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc, ...@@ -557,12 +543,12 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
ret = -EINVAL; ret = -EINVAL;
goto pipe_set_base_exit; goto pipe_set_base_exit;
} }
REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr);
REG_WRITE(dspbase, offset); REG_WRITE(map->base, offset);
REG_READ(dspbase); REG_READ(map->base);
REG_WRITE(dspsurf, start); REG_WRITE(map->surf, start);
REG_READ(dspsurf); REG_READ(map->surf);
pipe_set_base_exit: pipe_set_base_exit:
gma_power_end(dev); gma_power_end(dev);
......
drivers/gpu/drm/gma500/oaktrail_device.c
浏览文件 @ 213a8434
...@@ -475,7 +475,7 @@ static const struct psb_offset oaktrail_regmap[2] = { ...@@ -475,7 +475,7 @@ static const struct psb_offset oaktrail_regmap[2] = {
.size = DSPASIZE, .size = DSPASIZE,
.pos = DSPAPOS, .pos = DSPAPOS,
.surf = DSPASURF, .surf = DSPASURF,
.addr = DSPABASE, .addr = MRST_DSPABASE,
.status = PIPEASTAT, .status = PIPEASTAT,
.linoff = DSPALINOFF, .linoff = DSPALINOFF,
.tileoff = DSPATILEOFF, .tileoff = DSPATILEOFF,
......
drivers/gpu/drm/gma500/psb_intel_display.c
浏览文件 @ 213a8434
...@@ -337,15 +337,12 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc, ...@@ -337,15 +337,12 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
int x, int y, struct drm_framebuffer *old_fb) int x, int y, struct drm_framebuffer *old_fb)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
/* struct drm_i915_master_private *master_priv; */ struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
const struct psb_offset *map = &dev_priv->regmap[pipe];
unsigned long start, offset; unsigned long start, offset;
int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
u32 dspcntr; u32 dspcntr;
int ret = 0; int ret = 0;
...@@ -367,9 +364,9 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc, ...@@ -367,9 +364,9 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
REG_WRITE(dspstride, crtc->fb->pitches[0]); REG_WRITE(map->stride, crtc->fb->pitches[0]);
dspcntr = REG_READ(dspcntr_reg); dspcntr = REG_READ(map->cntr);
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
switch (crtc->fb->bits_per_pixel) { switch (crtc->fb->bits_per_pixel) {
...@@ -392,18 +389,10 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc, ...@@ -392,18 +389,10 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
psb_gtt_unpin(psbfb->gtt); psb_gtt_unpin(psbfb->gtt);
goto psb_intel_pipe_set_base_exit; goto psb_intel_pipe_set_base_exit;
} }
REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr);
if (0 /* FIXMEAC - check what PSB needs */) { REG_WRITE(map->base, start + offset);
REG_WRITE(dspbase, offset); REG_READ(map->base);
REG_READ(dspbase);
REG_WRITE(dspsurf, start);
REG_READ(dspsurf);
} else {
REG_WRITE(dspbase, start + offset);
REG_READ(dspbase);
}
psb_intel_pipe_cleaner: psb_intel_pipe_cleaner:
/* If there was a previous display we can now unpin it */ /* If there was a previous display we can now unpin it */
...@@ -424,14 +413,10 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc, ...@@ -424,14 +413,10 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
/* struct drm_i915_master_private *master_priv; */ struct drm_psb_private *dev_priv = dev->dev_private;
/* struct drm_i915_private *dev_priv = dev->dev_private; */
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; const struct psb_offset *map = &dev_priv->regmap[pipe];
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
u32 temp; u32 temp;
/* XXX: When our outputs are all unaware of DPMS modes other than off /* XXX: When our outputs are all unaware of DPMS modes other than off
...@@ -442,34 +427,34 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) ...@@ -442,34 +427,34 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_SUSPEND:
/* Enable the DPLL */ /* Enable the DPLL */
temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll);
if ((temp & DPLL_VCO_ENABLE) == 0) { if ((temp & DPLL_VCO_ENABLE) == 0) {
REG_WRITE(dpll_reg, temp); REG_WRITE(map->dpll, temp);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
} }
/* Enable the pipe */ /* Enable the pipe */
temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf);
if ((temp & PIPEACONF_ENABLE) == 0) if ((temp & PIPEACONF_ENABLE) == 0)
REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
/* Enable the plane */ /* Enable the plane */
temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr);
if ((temp & DISPLAY_PLANE_ENABLE) == 0) { if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr,
temp | DISPLAY_PLANE_ENABLE); temp | DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */ /* Flush the plane changes */
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_WRITE(map->base, REG_READ(map->base));
} }
psb_intel_crtc_load_lut(crtc); psb_intel_crtc_load_lut(crtc);
...@@ -487,29 +472,29 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) ...@@ -487,29 +472,29 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
/* Disable display plane */ /* Disable display plane */
temp = REG_READ(dspcntr_reg); temp = REG_READ(map->cntr);
if ((temp & DISPLAY_PLANE_ENABLE) != 0) { if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
REG_WRITE(dspcntr_reg, REG_WRITE(map->cntr,
temp & ~DISPLAY_PLANE_ENABLE); temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */ /* Flush the plane changes */
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); REG_WRITE(map->base, REG_READ(map->base));
REG_READ(dspbase_reg); REG_READ(map->base);
} }
/* Next, disable display pipes */ /* Next, disable display pipes */
temp = REG_READ(pipeconf_reg); temp = REG_READ(map->conf);
if ((temp & PIPEACONF_ENABLE) != 0) { if ((temp & PIPEACONF_ENABLE) != 0) {
REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
REG_READ(pipeconf_reg); REG_READ(map->conf);
} }
/* Wait for vblank for the disable to take effect. */ /* Wait for vblank for the disable to take effect. */
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
temp = REG_READ(dpll_reg); temp = REG_READ(map->dpll);
if ((temp & DPLL_VCO_ENABLE) != 0) { if ((temp & DPLL_VCO_ENABLE) != 0) {
REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
} }
/* Wait for the clocks to turn off. */ /* Wait for the clocks to turn off. */
...@@ -589,22 +574,11 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, ...@@ -589,22 +574,11 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
struct drm_framebuffer *old_fb) struct drm_framebuffer *old_fb)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
int fp_reg = (pipe == 0) ? FPA0 : FPB0; const struct psb_offset *map = &dev_priv->regmap[pipe];
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
int refclk; int refclk;
struct psb_intel_clock_t clock; struct psb_intel_clock_t clock;
u32 dpll = 0, fp = 0, dspcntr, pipeconf; u32 dpll = 0, fp = 0, dspcntr, pipeconf;
...@@ -690,7 +664,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, ...@@ -690,7 +664,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
dpll |= PLL_REF_INPUT_DREFCLK; dpll |= PLL_REF_INPUT_DREFCLK;
/* setup pipeconf */ /* setup pipeconf */
pipeconf = REG_READ(pipeconf_reg); pipeconf = REG_READ(map->conf);
/* Set up the display plane register */ /* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE; dspcntr = DISPPLANE_GAMMA_ENABLE;
...@@ -712,9 +686,9 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, ...@@ -712,9 +686,9 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
drm_mode_debug_printmodeline(mode); drm_mode_debug_printmodeline(mode);
if (dpll & DPLL_VCO_ENABLE) { if (dpll & DPLL_VCO_ENABLE) {
REG_WRITE(fp_reg, fp); REG_WRITE(map->fp0, fp);
REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
REG_READ(dpll_reg); REG_READ(map->dpll);
udelay(150); udelay(150);
} }
...@@ -747,45 +721,45 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, ...@@ -747,45 +721,45 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
REG_READ(LVDS); REG_READ(LVDS);
} }
REG_WRITE(fp_reg, fp); REG_WRITE(map->fp0, fp);
REG_WRITE(dpll_reg, dpll); REG_WRITE(map->dpll, dpll);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
/* write it again -- the BIOS does, after all */ /* write it again -- the BIOS does, after all */
REG_WRITE(dpll_reg, dpll); REG_WRITE(map->dpll, dpll);
REG_READ(dpll_reg); REG_READ(map->dpll);
/* Wait for the clocks to stabilize. */ /* Wait for the clocks to stabilize. */
udelay(150); udelay(150);
REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
((adjusted_mode->crtc_htotal - 1) << 16)); ((adjusted_mode->crtc_htotal - 1) << 16));
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
((adjusted_mode->crtc_hblank_end - 1) << 16)); ((adjusted_mode->crtc_hblank_end - 1) << 16));
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
((adjusted_mode->crtc_hsync_end - 1) << 16)); ((adjusted_mode->crtc_hsync_end - 1) << 16));
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
((adjusted_mode->crtc_vtotal - 1) << 16)); ((adjusted_mode->crtc_vtotal - 1) << 16));
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
((adjusted_mode->crtc_vblank_end - 1) << 16)); ((adjusted_mode->crtc_vblank_end - 1) << 16));
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16)); ((adjusted_mode->crtc_vsync_end - 1) << 16));
/* pipesrc and dspsize control the size that is scaled from, /* pipesrc and dspsize control the size that is scaled from,
* which should always be the user's requested size. * which should always be the user's requested size.
*/ */
REG_WRITE(dspsize_reg, REG_WRITE(map->size,
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
REG_WRITE(dsppos_reg, 0); REG_WRITE(map->pos, 0);
REG_WRITE(pipesrc_reg, REG_WRITE(map->src,
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
REG_WRITE(pipeconf_reg, pipeconf); REG_WRITE(map->conf, pipeconf);
REG_READ(pipeconf_reg); REG_READ(map->conf);
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
REG_WRITE(dspcntr_reg, dspcntr); REG_WRITE(map->cntr, dspcntr);
/* Flush the plane changes */ /* Flush the plane changes */
crtc_funcs->mode_set_base(crtc, x, y, old_fb); crtc_funcs->mode_set_base(crtc, x, y, old_fb);
...@@ -801,7 +775,8 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc) ...@@ -801,7 +775,8 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int palreg = PALETTE_A; const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
int palreg = map->palette;
int i; int i;
/* The clocks have to be on to load the palette. */ /* The clocks have to be on to load the palette. */
...@@ -810,12 +785,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc) ...@@ -810,12 +785,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
switch (psb_intel_crtc->pipe) { switch (psb_intel_crtc->pipe) {
case 0: case 0:
break;
case 1: case 1:
palreg = PALETTE_B;
break;
case 2:
palreg = PALETTE_C;
break; break;
default: default:
dev_err(dev->dev, "Illegal Pipe Number.\n"); dev_err(dev->dev, "Illegal Pipe Number.\n");
...@@ -853,11 +823,10 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc) ...@@ -853,11 +823,10 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
static void psb_intel_crtc_save(struct drm_crtc *crtc) static void psb_intel_crtc_save(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
/* struct drm_psb_private *dev_priv = struct drm_psb_private *dev_priv = dev->dev_private;
(struct drm_psb_private *)dev->dev_private; */
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
int pipeA = (psb_intel_crtc->pipe == 0); const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
uint32_t paletteReg; uint32_t paletteReg;
int i; int i;
...@@ -866,27 +835,27 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc) ...@@ -866,27 +835,27 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc)
return; return;
} }
crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR); crtc_state->saveDSPCNTR = REG_READ(map->cntr);
crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF); crtc_state->savePIPECONF = REG_READ(map->conf);
crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC); crtc_state->savePIPESRC = REG_READ(map->src);
crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0); crtc_state->saveFP0 = REG_READ(map->fp0);
crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1); crtc_state->saveFP1 = REG_READ(map->fp1);
crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B); crtc_state->saveDPLL = REG_READ(map->dpll);
crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B); crtc_state->saveHTOTAL = REG_READ(map->htotal);
crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B); crtc_state->saveHBLANK = REG_READ(map->hblank);
crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B); crtc_state->saveHSYNC = REG_READ(map->hsync);
crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B); crtc_state->saveVTOTAL = REG_READ(map->vtotal);
crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B); crtc_state->saveVBLANK = REG_READ(map->vblank);
crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B); crtc_state->saveVSYNC = REG_READ(map->vsync);
crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE); crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
/*NOTE: DSPSIZE DSPPOS only for psb*/ /*NOTE: DSPSIZE DSPPOS only for psb*/
crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE); crtc_state->saveDSPSIZE = REG_READ(map->size);
crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS); crtc_state->saveDSPPOS = REG_READ(map->pos);
crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE); crtc_state->saveDSPBASE = REG_READ(map->base);
paletteReg = pipeA ? PALETTE_A : PALETTE_B; paletteReg = map->palette;
for (i = 0; i < 256; ++i) for (i = 0; i < 256; ++i)
crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
} }
...@@ -897,12 +866,10 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc) ...@@ -897,12 +866,10 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc)
static void psb_intel_crtc_restore(struct drm_crtc *crtc) static void psb_intel_crtc_restore(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
/* struct drm_psb_private * dev_priv = struct drm_psb_private *dev_priv = dev->dev_private;
(struct drm_psb_private *)dev->dev_private; */
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
/* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */ const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
int pipeA = (psb_intel_crtc->pipe == 0);
uint32_t paletteReg; uint32_t paletteReg;
int i; int i;
...@@ -912,45 +879,45 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc) ...@@ -912,45 +879,45 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc)
} }
if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
REG_WRITE(pipeA ? DPLL_A : DPLL_B, REG_WRITE(map->dpll,
crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
REG_READ(pipeA ? DPLL_A : DPLL_B); REG_READ(map->dpll);
udelay(150); udelay(150);
} }
REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0); REG_WRITE(map->fp0, crtc_state->saveFP0);
REG_READ(pipeA ? FPA0 : FPB0); REG_READ(map->fp0);
REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1); REG_WRITE(map->fp1, crtc_state->saveFP1);
REG_READ(pipeA ? FPA1 : FPB1); REG_READ(map->fp1);
REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL); REG_WRITE(map->dpll, crtc_state->saveDPLL);
REG_READ(pipeA ? DPLL_A : DPLL_B); REG_READ(map->dpll);
udelay(150); udelay(150);
REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL); REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK); REG_WRITE(map->hblank, crtc_state->saveHBLANK);
REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC); REG_WRITE(map->hsync, crtc_state->saveHSYNC);
REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL); REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK); REG_WRITE(map->vblank, crtc_state->saveVBLANK);
REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC); REG_WRITE(map->vsync, crtc_state->saveVSYNC);
REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE); REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE); REG_WRITE(map->size, crtc_state->saveDSPSIZE);
REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS); REG_WRITE(map->pos, crtc_state->saveDSPPOS);
REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC); REG_WRITE(map->src, crtc_state->savePIPESRC);
REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); REG_WRITE(map->base, crtc_state->saveDSPBASE);
REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF); REG_WRITE(map->conf, crtc_state->savePIPECONF);
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR); REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE); REG_WRITE(map->base, crtc_state->saveDSPBASE);
psb_intel_wait_for_vblank(dev); psb_intel_wait_for_vblank(dev);
paletteReg = pipeA ? PALETTE_A : PALETTE_B; paletteReg = map->palette;
for (i = 0; i < 256; ++i) for (i = 0; i < 256; ++i)
REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
} }
...@@ -1114,20 +1081,21 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev, ...@@ -1114,20 +1081,21 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
struct drm_crtc *crtc) struct drm_crtc *crtc)
{ {
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct drm_psb_private *dev_priv = dev->dev_private;
int pipe = psb_intel_crtc->pipe; int pipe = psb_intel_crtc->pipe;
const struct psb_offset *map = &dev_priv->regmap[pipe];
u32 dpll; u32 dpll;
u32 fp; u32 fp;
struct psb_intel_clock_t clock; struct psb_intel_clock_t clock;
bool is_lvds; bool is_lvds;
struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); dpll = REG_READ(map->dpll);
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = REG_READ((pipe == 0) ? FPA0 : FPB0); fp = REG_READ(map->fp0);
else else
fp = REG_READ((pipe == 0) ? FPA1 : FPB1); fp = REG_READ(map->fp1);
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
gma_power_end(dev); gma_power_end(dev);
} else { } else {
...@@ -1197,12 +1165,13 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, ...@@ -1197,12 +1165,13 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
int vsync; int vsync;
struct drm_psb_private *dev_priv = dev->dev_private; struct drm_psb_private *dev_priv = dev->dev_private;
struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
const struct psb_offset *map = &dev_priv->regmap[pipe];
if (gma_power_begin(dev, false)) { if (gma_power_begin(dev, false)) {
htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); htot = REG_READ(map->htotal);
hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); hsync = REG_READ(map->hsync);
vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); vtot = REG_READ(map->vtotal);
vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); vsync = REG_READ(map->vsync);
gma_power_end(dev); gma_power_end(dev);
} else { } else {
htot = p->htotal; htot = p->htotal;
......
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