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kernel_linux
“67b0ad574b5ee90f8ea58196ff8a7f3780b75365”上不存在“arch/m32r/include/asm/bitops.h”
提交 0b8765c6 编写于 作者: J Jesse Barnes 提交者： Chris Wilson
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drm/i915: split i9xx CRTC enable/disable code 

So we can use it for CRTC prepare/commit.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
上级 6be4a607
隐藏空白更改
内联 并排
Showing with 103 addition and 82 deletion
drivers/gpu/drm/i915/intel_display.c
浏览文件 @ 0b8765c6
...@@ -2262,7 +2262,7 @@ static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) ...@@ -2262,7 +2262,7 @@ static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
*/ */
} }
static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) static void i9xx_crtc_enable(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
...@@ -2275,97 +2275,118 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) ...@@ -2275,97 +2275,118 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
u32 temp; u32 temp;
/* XXX: When our outputs are all unaware of DPMS modes other than off /* Enable the DPLL */
* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. temp = I915_READ(dpll_reg);
*/ if ((temp & DPLL_VCO_ENABLE) == 0) {
switch (mode) { I915_WRITE(dpll_reg, temp);
case DRM_MODE_DPMS_ON: I915_READ(dpll_reg);
case DRM_MODE_DPMS_STANDBY: /* Wait for the clocks to stabilize. */
case DRM_MODE_DPMS_SUSPEND: udelay(150);
/* Enable the DPLL */ I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
temp = I915_READ(dpll_reg); I915_READ(dpll_reg);
if ((temp & DPLL_VCO_ENABLE) == 0) { /* Wait for the clocks to stabilize. */
I915_WRITE(dpll_reg, temp); udelay(150);
I915_READ(dpll_reg); I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
/* Wait for the clocks to stabilize. */ I915_READ(dpll_reg);
udelay(150); /* Wait for the clocks to stabilize. */
I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); udelay(150);
I915_READ(dpll_reg); }
/* Wait for the clocks to stabilize. */
udelay(150);
I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
I915_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
udelay(150);
}
/* Enable the pipe */ /* Enable the pipe */
temp = I915_READ(pipeconf_reg); temp = I915_READ(pipeconf_reg);
if ((temp & PIPEACONF_ENABLE) == 0) if ((temp & PIPEACONF_ENABLE) == 0)
I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
/* Enable the plane */
temp = I915_READ(dspcntr_reg);
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
}
intel_crtc_load_lut(crtc); /* Enable the plane */
temp = I915_READ(dspcntr_reg);
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
}
if ((IS_I965G(dev) || plane == 0)) intel_crtc_load_lut(crtc);
intel_update_fbc(crtc, &crtc->mode);
/* Give the overlay scaler a chance to enable if it's on this pipe */ if ((IS_I965G(dev) || plane == 0))
intel_crtc_dpms_overlay(intel_crtc, true); intel_update_fbc(crtc, &crtc->mode);
break;
case DRM_MODE_DPMS_OFF:
/* Give the overlay scaler a chance to disable if it's on this pipe */
intel_crtc_dpms_overlay(intel_crtc, false);
drm_vblank_off(dev, pipe);
if (dev_priv->cfb_plane == plane &&
dev_priv->display.disable_fbc)
dev_priv->display.disable_fbc(dev);
/* Disable display plane */
temp = I915_READ(dspcntr_reg);
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
I915_READ(dspbase_reg);
}
if (!IS_I9XX(dev)) { /* Give the overlay scaler a chance to enable if it's on this pipe */
/* Wait for vblank for the disable to take effect */ intel_crtc_dpms_overlay(intel_crtc, true);
intel_wait_for_vblank_off(dev, pipe); }
}
/* Don't disable pipe A or pipe A PLLs if needed */ static void i9xx_crtc_disable(struct drm_crtc *crtc)
if (pipeconf_reg == PIPEACONF && {
(dev_priv->quirks & QUIRK_PIPEA_FORCE)) struct drm_device *dev = crtc->dev;
goto skip_pipe_off; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
u32 temp;
/* Next, disable display pipes */ /* Give the overlay scaler a chance to disable if it's on this pipe */
temp = I915_READ(pipeconf_reg); intel_crtc_dpms_overlay(intel_crtc, false);
if ((temp & PIPEACONF_ENABLE) != 0) { drm_vblank_off(dev, pipe);
I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
I915_READ(pipeconf_reg); if (dev_priv->cfb_plane == plane &&
} dev_priv->display.disable_fbc)
dev_priv->display.disable_fbc(dev);
/* Wait for vblank for the disable to take effect. */ /* Disable display plane */
temp = I915_READ(dspcntr_reg);
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
I915_READ(dspbase_reg);
}
if (!IS_I9XX(dev)) {
/* Wait for vblank for the disable to take effect */
intel_wait_for_vblank_off(dev, pipe); intel_wait_for_vblank_off(dev, pipe);
}
temp = I915_READ(dpll_reg); /* Don't disable pipe A or pipe A PLLs if needed */
if ((temp & DPLL_VCO_ENABLE) != 0) { if (pipeconf_reg == PIPEACONF &&
I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); (dev_priv->quirks & QUIRK_PIPEA_FORCE))
I915_READ(dpll_reg); goto skip_pipe_off;
}
skip_pipe_off: /* Next, disable display pipes */
/* Wait for the clocks to turn off. */ temp = I915_READ(pipeconf_reg);
udelay(150); if ((temp & PIPEACONF_ENABLE) != 0) {
I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
I915_READ(pipeconf_reg);
}
/* Wait for vblank for the disable to take effect. */
intel_wait_for_vblank_off(dev, pipe);
temp = I915_READ(dpll_reg);
if ((temp & DPLL_VCO_ENABLE) != 0) {
I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
I915_READ(dpll_reg);
}
skip_pipe_off:
/* Wait for the clocks to turn off. */
udelay(150);
}
static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
{
/* XXX: When our outputs are all unaware of DPMS modes other than off
* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
*/
switch (mode) {
case DRM_MODE_DPMS_ON:
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
i9xx_crtc_enable(crtc);
break;
case DRM_MODE_DPMS_OFF:
i9xx_crtc_disable(crtc);
break; break;
} }
} }
......
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