After the common MIPS CPU interrupt controller (for irq0-7) was introduced
the Lasat boards didn't get their interrupts right, so nothing worked. The
old routines need to be offset by the new 8 hardware interrupts common to
all MIPS CPU's.
Signed-off-by: NThomas Horsten <thomas@horsten.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>