The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
according to the i.MX6q/sdl reference manuals.  This clock is actually the
gate for several clocks, including the ipg clock's output.  The MIPI DSI host
controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
the APB clock signal .  In order to gate/ungate the ipg clock, this patch adds
a new shared clock gate named as "mipi_ipg".
Signed-off-by: NLiu Ying <Ying.Liu@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>