These two are both ARMv7 SoCs.  They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.

Refer to commit a092f2b1 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>