Correct enet clock gates as below:

CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK

Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.

Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>