Add optional output clock DT property to enable PLL reset when a clock
output is enabled.

Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: NSergej Sawazki <sergej@taudac.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>