As far back as I can see (which right now is a draft of the v1.2 spec
dating from September 2008), bits 24-31 of the Extended Capability Register
have already been reserved. I have no idea why anyone ever thought there
would be multiple sets of IOTLB registers, but we've never supported them
and all we do is make sure we map enough MMIO space for them.

Kill it dead. Those bits do actually have a different meaning now.
Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>