The interrupt decode register is not being cleared if an invalid interrupt
arises.  Clear the decode register in this case.
Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>