The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
and v116/216) contains a modified version of the PL180 MMCI, with
PeriphID Configuration value changed to 0x2.

This version adds an optional "hardware flow control" feature. When
enabled MMC card clock will be automatically disabled when FIFO is
about to over/underflow and re-enabled once the host retrieved some
data. This makes the controller immune to over/underrun errors caused
by big interrupt handling latencies.

This patch adds relevant device variant in the driver.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>