The cam_mclk clock is generated through the following clocks chain:

dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk

As dpll4_m5 and dpll4_m5x2 do not driver any clock other than cam_mclk,
back-propagate the cam_clk rate changes up to dpll4_m5.
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: NMike Turquette <mturquette@linaro.org>
Acked-by: NSakari Ailus <sakari.ailus@iki.fi>
Tested-by: NSakari Ailus <sakari.ailus@iki.fi>