Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.
Signed-off-by: NBill Huang <bilhuang@nvidia.com>
Signed-off-by: NRhyland Klein <rklein@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>