hw.c 64.6 KB
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/*
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 * Copyright (c) 2008-2010 Atheros Communications Inc.
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 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/io.h>
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#include <linux/slab.h>
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#include <asm/unaligned.h>

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#include "hw.h"
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#include "hw-ops.h"
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#include "rc.h"
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#include "ar9003_mac.h"
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static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
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MODULE_AUTHOR("Atheros Communications");
MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
MODULE_LICENSE("Dual BSD/GPL");

static int __init ath9k_init(void)
{
	return 0;
}
module_init(ath9k_init);

static void __exit ath9k_exit(void)
{
	return;
}
module_exit(ath9k_exit);

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/* Private hardware callbacks */

static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_cal_settings(ah);
}

static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
{
	ath9k_hw_private_ops(ah)->init_mode_regs(ah);
}

static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	return priv_ops->macversion_supported(ah->hw_version.macVersion);
}

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static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
					struct ath9k_channel *chan)
{
	return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
}

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static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
{
	if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
		return;

	ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
}

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static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
{
	/* You will not have this callback if using the old ANI */
	if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
		return;

	ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
}

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/********************/
/* Helper Functions */
/********************/
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static void ath9k_hw_set_clockrate(struct ath_hw *ah)
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{
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	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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	struct ath_common *common = ath9k_hw_common(ah);
	unsigned int clockrate;
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	if (!ah->curchan) /* should really check for CCK instead */
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		clockrate = ATH9K_CLOCK_RATE_CCK;
	else if (conf->channel->band == IEEE80211_BAND_2GHZ)
		clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
	else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
		clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
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	else
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		clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;

	if (conf_is_ht40(conf))
		clockrate *= 2;

	common->clockrate = clockrate;
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}

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static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	return usecs * common->clockrate;
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}
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bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
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{
	int i;

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	BUG_ON(timeout < AH_TIME_QUANTUM);

	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
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		if ((REG_READ(ah, reg) & mask) == val)
			return true;

		udelay(AH_TIME_QUANTUM);
	}
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	ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
		  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
		  timeout, reg, REG_READ(ah, reg), mask, val);
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	return false;
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}
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EXPORT_SYMBOL(ath9k_hw_wait);
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u32 ath9k_hw_reverse_bits(u32 val, u32 n)
{
	u32 retval;
	int i;

	for (i = 0, retval = 0; i < n; i++) {
		retval = (retval << 1) | (val & 1);
		val >>= 1;
	}
	return retval;
}

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bool ath9k_get_channel_edges(struct ath_hw *ah,
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			     u16 flags, u16 *low,
			     u16 *high)
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{
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	struct ath9k_hw_capabilities *pCap = &ah->caps;
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	if (flags & CHANNEL_5GHZ) {
		*low = pCap->low_5ghz_chan;
		*high = pCap->high_5ghz_chan;
		return true;
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	}
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	if ((flags & CHANNEL_2GHZ)) {
		*low = pCap->low_2ghz_chan;
		*high = pCap->high_2ghz_chan;
		return true;
	}
	return false;
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}

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u16 ath9k_hw_computetxtime(struct ath_hw *ah,
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			   u8 phy, int kbps,
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			   u32 frameLen, u16 rateix,
			   bool shortPreamble)
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{
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	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
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	if (kbps == 0)
		return 0;
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	switch (phy) {
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	case WLAN_RC_PHY_CCK:
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		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
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		if (shortPreamble)
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			phyTime >>= 1;
		numBits = frameLen << 3;
		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
		break;
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	case WLAN_RC_PHY_OFDM:
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		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_QUARTER
				+ OFDM_PREAMBLE_TIME_QUARTER
				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
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		} else if (ah->curchan &&
			   IS_CHAN_HALF_RATE(ah->curchan)) {
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			bitsPerSymbol =	(kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME_HALF +
				OFDM_PREAMBLE_TIME_HALF
				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
		} else {
			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
			numBits = OFDM_PLCP_BITS + (frameLen << 3);
			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
				+ (numSymbols * OFDM_SYMBOL_TIME);
		}
		break;
	default:
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		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
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			  "Unknown phy %u (rate ix %u)\n", phy, rateix);
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		txTime = 0;
		break;
	}
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	return txTime;
}
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EXPORT_SYMBOL(ath9k_hw_computetxtime);
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void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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				  struct ath9k_channel *chan,
				  struct chan_centers *centers)
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{
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	int8_t extoff;
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	if (!IS_CHAN_HT40(chan)) {
		centers->ctl_center = centers->ext_center =
			centers->synth_center = chan->channel;
		return;
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	}

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	if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
	    (chan->chanmode == CHANNEL_G_HT40PLUS)) {
		centers->synth_center =
			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
		extoff = 1;
	} else {
		centers->synth_center =
			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
		extoff = -1;
	}
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	centers->ctl_center =
		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
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	/* 25 MHz spacing is supported by hw but not on upper layers */
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	centers->ext_center =
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		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
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}

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/******************/
/* Chip Revisions */
/******************/

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static void ath9k_hw_read_revisions(struct ath_hw *ah)
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{
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	u32 val;
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	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
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	if (val == 0xFF) {
		val = REG_READ(ah, AR_SREV);
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		ah->hw_version.macVersion =
			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
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		ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
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	} else {
		if (!AR_SREV_9100(ah))
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			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
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		ah->hw_version.macRev = val & AR_SREV_REVISION;
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		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
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			ah->is_pciexpress = true;
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	}
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}

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/************************************/
/* HW Attach, Detach, Init Routines */
/************************************/

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static void ath9k_hw_disablepcie(struct ath_hw *ah)
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{
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	if (AR_SREV_9100(ah))
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		return;
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	ENABLE_REGWRITE_BUFFER(ah);

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	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
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	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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	REGWRITE_BUFFER_FLUSH(ah);
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}

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/* This should work for all families including legacy */
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static bool ath9k_hw_chip_test(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 regAddr[2] = { AR_STA_ID0 };
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	u32 regHold[2];
	u32 patternData[4] = { 0x55555555,
			       0xaaaaaaaa,
			       0x66666666,
			       0x99999999 };
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	int i, j, loop_max;
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	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		loop_max = 2;
		regAddr[1] = AR_PHY_BASE + (8 << 2);
	} else
		loop_max = 1;

	for (i = 0; i < loop_max; i++) {
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		u32 addr = regAddr[i];
		u32 wrData, rdData;
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		regHold[i] = REG_READ(ah, addr);
		for (j = 0; j < 0x100; j++) {
			wrData = (j << 16) | j;
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (rdData != wrData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
		}
		for (j = 0; j < 4; j++) {
			wrData = patternData[j];
			REG_WRITE(ah, addr, wrData);
			rdData = REG_READ(ah, addr);
			if (wrData != rdData) {
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				ath_print(common, ATH_DBG_FATAL,
					  "address test failed "
					  "addr: 0x%08x - wr:0x%08x != "
					  "rd:0x%08x\n",
					  addr, wrData, rdData);
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				return false;
			}
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		}
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		REG_WRITE(ah, regAddr[i], regHold[i]);
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	}
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	udelay(100);
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	return true;
}

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static void ath9k_hw_init_config(struct ath_hw *ah)
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{
	int i;
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	ah->config.dma_beacon_response_time = 2;
	ah->config.sw_beacon_response_time = 10;
	ah->config.additional_swba_backoff = 0;
	ah->config.ack_6mb = 0x0;
	ah->config.cwm_ignore_extcca = 0;
	ah->config.pcie_powersave_enable = 0;
	ah->config.pcie_clock_req = 0;
	ah->config.pcie_waen = 0;
	ah->config.analog_shiftreg = 1;
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	ah->config.enable_ani = true;
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	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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		ah->config.spurchans[i][0] = AR_NO_SPUR;
		ah->config.spurchans[i][1] = AR_NO_SPUR;
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	}

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	if (ah->hw_version.devid != AR2427_DEVID_PCIE)
		ah->config.ht_enable = 1;
	else
		ah->config.ht_enable = 0;

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	ah->config.rx_intr_mitigation = true;
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	ah->config.pcieSerDesWrite = true;
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	/*
	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
	 * This means we use it for all AR5416 devices, and the few
	 * minor PCI AR9280 devices out there.
	 *
	 * Serialization is required because these devices do not handle
	 * well the case of two concurrent reads/writes due to the latency
	 * involved. During one read/write another read/write can be issued
	 * on another CPU while the previous read/write may still be working
	 * on our hardware, if we hit this case the hardware poops in a loop.
	 * We prevent this by serializing reads and writes.
	 *
	 * This issue is not present on PCI-Express devices or pre-AR5416
	 * devices (legacy, 802.11abg).
	 */
	if (num_possible_cpus() > 1)
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		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
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}

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static void ath9k_hw_init_defaults(struct ath_hw *ah)
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{
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	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	regulatory->country_code = CTRY_DEFAULT;
	regulatory->power_limit = MAX_RATE_POWER;
	regulatory->tp_scale = ATH9K_TP_SCALE_MAX;

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	ah->hw_version.magic = AR5416_MAGIC;
	ah->hw_version.subvendorid = 0;
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	ah->ah_flags = 0;
	if (!AR_SREV_9100(ah))
		ah->ah_flags = AH_USE_EEPROM;

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	ah->atim_window = 0;
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	ah->sta_id1_defaults =
		AR_STA_ID1_CRPT_MIC_ENABLE |
		AR_STA_ID1_MCAST_KSRCH;
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	ah->beacon_interval = 100;
	ah->enable_32kHz_clock = DONT_USE_32KHZ;
	ah->slottime = (u32) -1;
	ah->globaltxtimeout = (u32) -1;
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	ah->power_mode = ATH9K_PM_UNDEFINED;
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}

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static int ath9k_hw_init_macaddr(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	u32 sum;
	int i;
	u16 eeval;
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	u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
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	sum = 0;
	for (i = 0; i < 3; i++) {
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		eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
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		sum += eeval;
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		common->macaddr[2 * i] = eeval >> 8;
		common->macaddr[2 * i + 1] = eeval & 0xff;
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	}
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	if (sum == 0 || sum == 0xffff * 3)
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		return -EADDRNOTAVAIL;

	return 0;
}

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static int ath9k_hw_post_init(struct ath_hw *ah)
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{
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	int ecode;
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	if (!AR_SREV_9271(ah)) {
		if (!ath9k_hw_chip_test(ah))
			return -ENODEV;
	}
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	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		ecode = ar9002_hw_rf_claim(ah);
		if (ecode != 0)
			return ecode;
	}
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	ecode = ath9k_hw_eeprom_init(ah);
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	if (ecode != 0)
		return ecode;
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	ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
		  "Eeprom VER: %d, REV: %d\n",
		  ah->eep_ops->get_eeprom_ver(ah),
		  ah->eep_ops->get_eeprom_rev(ah));
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	ecode = ath9k_hw_rf_alloc_ext_banks(ah);
	if (ecode) {
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed allocating banks for "
			  "external radio\n");
		return ecode;
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	}
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	if (!AR_SREV_9100(ah)) {
		ath9k_hw_ani_setup(ah);
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		ath9k_hw_ani_init(ah);
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	}

	return 0;
}

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static void ath9k_hw_attach_ops(struct ath_hw *ah)
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{
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	if (AR_SREV_9300_20_OR_LATER(ah))
		ar9003_hw_attach_ops(ah);
	else
		ar9002_hw_attach_ops(ah);
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}

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/* Called for all hardware families */
static int __ath9k_hw_init(struct ath_hw *ah)
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{
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	struct ath_common *common = ath9k_hw_common(ah);
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	int r = 0;
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	if (ah->hw_version.devid == AR5416_AR9100_DEVID)
		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
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	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
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		ath_print(common, ATH_DBG_FATAL,
			  "Couldn't reset chip\n");
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		return -EIO;
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	}

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	ath9k_hw_init_defaults(ah);
	ath9k_hw_init_config(ah);

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	ath9k_hw_attach_ops(ah);
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	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
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		ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
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		return -EIO;
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	}

	if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
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		    ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
		     !ah->is_pciexpress)) {
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			ah->config.serialize_regmode =
				SER_REG_MODE_ON;
		} else {
			ah->config.serialize_regmode =
				SER_REG_MODE_OFF;
		}
	}

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	ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
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		ah->config.serialize_regmode);

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	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;

551
	if (!ath9k_hw_macversion_supported(ah)) {
552 553 554 555
		ath_print(common, ATH_DBG_FATAL,
			  "Mac Chip Rev 0x%02x.%x is not supported by "
			  "this driver\n", ah->hw_version.macVersion,
			  ah->hw_version.macRev);
556
		return -EOPNOTSUPP;
557 558
	}

559
	if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
560 561
		ah->is_pciexpress = false;

562 563 564 565
	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
	ath9k_hw_init_cal_settings(ah);

	ah->ani_function = ATH9K_ANI_ALL;
566
	if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
567
		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
568 569
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
570 571 572

	ath9k_hw_init_mode_regs(ah);

573 574 575 576 577 578 579 580 581
	/*
	 * Read back AR_WA into a permanent copy and set bits 14 and 17.
	 * We need to do this to avoid RMW of this register. We cannot
	 * read the reg when chip is asleep.
	 */
	ah->WARegVal = REG_READ(ah, AR_WA);
	ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
			 AR_WA_ASPM_TIMER_BASED_DISABLE);

582
	if (ah->is_pciexpress)
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		ath9k_hw_configpcipowersave(ah, 0, 0);
584 585 586
	else
		ath9k_hw_disablepcie(ah);

587 588
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ar9002_hw_cck_chan14_spread(ah);
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589

590
	r = ath9k_hw_post_init(ah);
591
	if (r)
592
		return r;
593 594

	ath9k_hw_init_mode_gain_regs(ah);
595 596 597 598
	r = ath9k_hw_fill_cap_info(ah);
	if (r)
		return r;

599 600
	r = ath9k_hw_init_macaddr(ah);
	if (r) {
601 602
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to initialize MAC address\n");
603
		return r;
604 605
	}

606
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
607
		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
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	else
609
		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
610

611
	ah->bb_watchdog_timeout_ms = 25;
612

613 614
	common->state = ATH_HW_INITIALIZED;

615
	return 0;
616 617
}

618
int ath9k_hw_init(struct ath_hw *ah)
619
{
620 621
	int ret;
	struct ath_common *common = ath9k_hw_common(ah);
622

623 624 625 626 627 628 629 630 631
	/* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
	switch (ah->hw_version.devid) {
	case AR5416_DEVID_PCI:
	case AR5416_DEVID_PCIE:
	case AR5416_AR9100_DEVID:
	case AR9160_DEVID_PCI:
	case AR9280_DEVID_PCI:
	case AR9280_DEVID_PCIE:
	case AR9285_DEVID_PCIE:
632 633
	case AR9287_DEVID_PCI:
	case AR9287_DEVID_PCIE:
634
	case AR2427_DEVID_PCIE:
635
	case AR9300_DEVID_PCIE:
636 637 638 639 640 641 642 643 644
		break;
	default:
		if (common->bus_ops->ath_bus_type == ATH_USB)
			break;
		ath_print(common, ATH_DBG_FATAL,
			  "Hardware device ID 0x%04x not supported\n",
			  ah->hw_version.devid);
		return -EOPNOTSUPP;
	}
645

646 647 648 649 650 651 652
	ret = __ath9k_hw_init(ah);
	if (ret) {
		ath_print(common, ATH_DBG_FATAL,
			  "Unable to initialize hardware; "
			  "initialization status: %d\n", ret);
		return ret;
	}
653

654
	return 0;
655
}
656
EXPORT_SYMBOL(ath9k_hw_init);
657

658
static void ath9k_hw_init_qos(struct ath_hw *ah)
659
{
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	ENABLE_REGWRITE_BUFFER(ah);

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	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
664

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665 666 667 668 669 670 671 672 673 674
	REG_WRITE(ah, AR_QOS_NO_ACK,
		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));

	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
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675 676

	REGWRITE_BUFFER_FLUSH(ah);
677 678
}

679
static void ath9k_hw_init_pll(struct ath_hw *ah,
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680
			      struct ath9k_channel *chan)
681
{
682
	u32 pll = ath9k_hw_compute_pll_control(ah, chan);
683

684
	REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
685

686 687
	/* Switch the core clock for ar9271 to 117Mhz */
	if (AR_SREV_9271(ah)) {
688 689
		udelay(500);
		REG_WRITE(ah, 0x50040, 0x304);
690 691
	}

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	udelay(RTC_PLL_SETTLE_DELAY);

	REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
695 696
}

697
static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
698
					  enum nl80211_iftype opmode)
699
{
700
	u32 imr_reg = AR_IMR_TXERR |
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701 702 703 704
		AR_IMR_TXURN |
		AR_IMR_RXERR |
		AR_IMR_RXORN |
		AR_IMR_BCNMISC;
705

706 707 708 709 710 711
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		imr_reg |= AR_IMR_RXOK_HP;
		if (ah->config.rx_intr_mitigation)
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			imr_reg |= AR_IMR_RXOK_LP;
712

713 714 715 716 717 718
	} else {
		if (ah->config.rx_intr_mitigation)
			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
		else
			imr_reg |= AR_IMR_RXOK;
	}
719

720 721 722 723
	if (ah->config.tx_intr_mitigation)
		imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
	else
		imr_reg |= AR_IMR_TXOK;
724

725
	if (opmode == NL80211_IFTYPE_AP)
726
		imr_reg |= AR_IMR_MIB;
727

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728 729
	ENABLE_REGWRITE_BUFFER(ah);

730
	REG_WRITE(ah, AR_IMR, imr_reg);
731 732
	ah->imrs2_reg |= AR_IMR_S2_GTT;
	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
733

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734 735 736 737 738
	if (!AR_SREV_9100(ah)) {
		REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
		REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
		REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
	}
739

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740 741
	REGWRITE_BUFFER_FLUSH(ah);

742 743 744 745 746 747
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
		REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
		REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
	}
748 749
}

750
static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
751
{
752 753 754
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) 0xFFFF);
	REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
755 756
}

757
static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
758
{
759 760 761 762 763 764 765 766 767 768
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
}

static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
{
	u32 val = ath9k_hw_mac_to_clks(ah, us);
	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
769
}
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770

771
static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
772 773
{
	if (tu > 0xFFFF) {
774 775
		ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
			  "bad global tx timeout %u\n", tu);
776
		ah->globaltxtimeout = (u32) -1;
777 778 779
		return false;
	} else {
		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
780
		ah->globaltxtimeout = tu;
781 782 783 784
		return true;
	}
}

785
void ath9k_hw_init_global_settings(struct ath_hw *ah)
786
{
787 788
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
	int acktimeout;
789
	int slottime;
790 791
	int sifstime;

792 793
	ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
		  ah->misc_mode);
794

795
	if (ah->misc_mode != 0)
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		REG_WRITE(ah, AR_PCU_MISC,
797
			  REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
798 799 800 801 802 803

	if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
		sifstime = 16;
	else
		sifstime = 10;

804 805 806
	/* As defined by IEEE 802.11-2007 17.3.8.6 */
	slottime = ah->slottime + 3 * ah->coverage_class;
	acktimeout = slottime + sifstime;
807 808 809 810 811 812 813 814 815 816 817

	/*
	 * Workaround for early ACK timeouts, add an offset to match the
	 * initval's 64us ack timeout value.
	 * This was initially only meant to work around an issue with delayed
	 * BA frames in some implementations, but it has been found to fix ACK
	 * timeout issues in other cases as well.
	 */
	if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
		acktimeout += 64 - sifstime - ah->slottime;

818
	ath9k_hw_setslottime(ah, slottime);
819 820
	ath9k_hw_set_ack_timeout(ah, acktimeout);
	ath9k_hw_set_cts_timeout(ah, acktimeout);
821 822
	if (ah->globaltxtimeout != (u32) -1)
		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
S
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823
}
824
EXPORT_SYMBOL(ath9k_hw_init_global_settings);
S
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825

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826
void ath9k_hw_deinit(struct ath_hw *ah)
S
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827
{
828 829
	struct ath_common *common = ath9k_hw_common(ah);

S
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830
	if (common->state < ATH_HW_INITIALIZED)
831 832
		goto free_hw;

833
	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
834 835

free_hw:
836
	ath9k_hw_rf_free_ext_banks(ah);
S
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837
}
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838
EXPORT_SYMBOL(ath9k_hw_deinit);
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839 840 841 842 843

/*******/
/* INI */
/*******/

844
u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
845 846 847 848 849 850 851 852 853 854 855 856 857
{
	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);

	if (IS_CHAN_B(chan))
		ctl |= CTL_11B;
	else if (IS_CHAN_G(chan))
		ctl |= CTL_11G;
	else
		ctl |= CTL_11A;

	return ctl;
}

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858 859 860 861
/****************************************/
/* Reset and Channel Switching Routines */
/****************************************/

862
static inline void ath9k_hw_set_dma(struct ath_hw *ah)
S
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863
{
864
	struct ath_common *common = ath9k_hw_common(ah);
S
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865 866
	u32 regval;

S
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867 868
	ENABLE_REGWRITE_BUFFER(ah);

869 870 871
	/*
	 * set AHB_MODE not to do cacheline prefetches
	*/
872 873 874 875
	if (!AR_SREV_9300_20_OR_LATER(ah)) {
		regval = REG_READ(ah, AR_AHB_MODE);
		REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
	}
S
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876

877 878 879
	/*
	 * let mac dma reads be in 128 byte chunks
	 */
S
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880 881 882
	regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);

S
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883 884
	REGWRITE_BUFFER_FLUSH(ah);

885 886 887 888 889
	/*
	 * Restore TX Trigger Level to its pre-reset value.
	 * The initial value depends on whether aggregation is enabled, and is
	 * adjusted whenever underruns are detected.
	 */
890 891
	if (!AR_SREV_9300_20_OR_LATER(ah))
		REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
S
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892

S
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893
	ENABLE_REGWRITE_BUFFER(ah);
S
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894

895 896 897
	/*
	 * let mac dma writes be in 128 byte chunks
	 */
S
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898 899 900
	regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
	REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);

901 902 903
	/*
	 * Setup receive FIFO threshold to hold off TX activities
	 */
S
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904 905
	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);

906 907 908 909 910 911 912 913
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);

		ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
			ah->caps.rx_status_len);
	}

914 915 916 917
	/*
	 * reduce the number of usable entries in PCU TXBUF to avoid
	 * wrap around issues.
	 */
S
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918
	if (AR_SREV_9285(ah)) {
919 920 921 922
		/* For AR9285 the number of Fifos are reduced to half.
		 * So set the usable tx buf size also to half to
		 * avoid data/delimiter underruns
		 */
S
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923 924
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
925
	} else if (!AR_SREV_9271(ah)) {
S
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926 927 928
		REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
			  AR_PCU_TXBUF_CTRL_USABLE_SIZE);
	}
929

S
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930 931
	REGWRITE_BUFFER_FLUSH(ah);

932 933
	if (AR_SREV_9300_20_OR_LATER(ah))
		ath9k_hw_reset_txstatus_ring(ah);
S
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934 935
}

936
static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
S
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937 938 939 940 941 942
{
	u32 val;

	val = REG_READ(ah, AR_STA_ID1);
	val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
	switch (opmode) {
943
	case NL80211_IFTYPE_AP:
S
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944 945 946
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
			  | AR_STA_ID1_KSRCH_MODE);
		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
947
		break;
948
	case NL80211_IFTYPE_ADHOC:
949
	case NL80211_IFTYPE_MESH_POINT:
S
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950 951 952
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
			  | AR_STA_ID1_KSRCH_MODE);
		REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
953
		break;
954 955
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
S
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956
		REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
957
		break;
S
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958 959 960
	}
}

961 962
void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
				   u32 *coef_mantissa, u32 *coef_exponent)
S
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963 964 965 966 967 968 969 970 971 972 973 974 975 976 977
{
	u32 coef_exp, coef_man;

	for (coef_exp = 31; coef_exp > 0; coef_exp--)
		if ((coef_scaled >> coef_exp) & 0x1)
			break;

	coef_exp = 14 - (coef_exp - COEF_SCALE_S);

	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));

	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
	*coef_exponent = coef_exp - 16;
}

978
static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
S
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979 980 981 982
{
	u32 rst_flags;
	u32 tmpReg;

983 984 985 986 987 988 989 990
	if (AR_SREV_9100(ah)) {
		u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
		val &= ~AR_RTC_DERIVED_CLK_PERIOD;
		val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
		REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);
	}

S
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991 992
	ENABLE_REGWRITE_BUFFER(ah);

993 994 995 996 997
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

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998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

	if (AR_SREV_9100(ah)) {
		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
	} else {
		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
		if (tmpReg &
		    (AR_INTR_SYNC_LOCAL_TIMEOUT |
		     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1009
			u32 val;
S
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1010
			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1011 1012 1013 1014 1015 1016 1017

			val = AR_RC_HOSTIF;
			if (!AR_SREV_9300_20_OR_LATER(ah))
				val |= AR_RC_AHB;
			REG_WRITE(ah, AR_RC, val);

		} else if (!AR_SREV_9300_20_OR_LATER(ah))
S
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1018 1019 1020 1021 1022 1023 1024
			REG_WRITE(ah, AR_RC, AR_RC_AHB);

		rst_flags = AR_RTC_RC_MAC_WARM;
		if (type == ATH9K_RESET_COLD)
			rst_flags |= AR_RTC_RC_MAC_COLD;
	}

1025
	REG_WRITE(ah, AR_RTC_RC, rst_flags);
S
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1026 1027 1028

	REGWRITE_BUFFER_FLUSH(ah);

S
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1029 1030
	udelay(50);

1031
	REG_WRITE(ah, AR_RTC_RC, 0);
S
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1032
	if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1033 1034
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC stuck in MAC reset\n");
S
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1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046
		return false;
	}

	if (!AR_SREV_9100(ah))
		REG_WRITE(ah, AR_RC, 0);

	if (AR_SREV_9100(ah))
		udelay(50);

	return true;
}

1047
static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
S
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1048
{
S
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1049 1050
	ENABLE_REGWRITE_BUFFER(ah);

1051 1052 1053 1054 1055
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

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1056 1057 1058
	REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
		  AR_RTC_FORCE_WAKE_ON_INT);

1059
	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1060 1061
		REG_WRITE(ah, AR_RC, AR_RC_AHB);

1062
	REG_WRITE(ah, AR_RTC_RESET, 0);
1063
	udelay(2);
1064

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1065 1066
	REGWRITE_BUFFER_FLUSH(ah);

1067 1068 1069 1070
	if (!AR_SREV_9300_20_OR_LATER(ah))
		udelay(2);

	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1071 1072
		REG_WRITE(ah, AR_RC, 0);

1073
	REG_WRITE(ah, AR_RTC_RESET, 1);
S
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1074 1075 1076 1077

	if (!ath9k_hw_wait(ah,
			   AR_RTC_STATUS,
			   AR_RTC_STATUS_M,
S
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1078 1079
			   AR_RTC_STATUS_ON,
			   AH_WAIT_TIMEOUT)) {
1080 1081
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "RTC not waking up\n");
S
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1082
		return false;
1083 1084
	}

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1085 1086 1087 1088 1089
	ath9k_hw_read_revisions(ah);

	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
}

1090
static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
S
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1091
{
1092 1093 1094 1095 1096
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108
	REG_WRITE(ah, AR_RTC_FORCE_WAKE,
		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);

	switch (type) {
	case ATH9K_RESET_POWER_ON:
		return ath9k_hw_set_reset_power_on(ah);
	case ATH9K_RESET_WARM:
	case ATH9K_RESET_COLD:
		return ath9k_hw_set_reset(ah, type);
	default:
		return false;
	}
1109 1110
}

1111
static bool ath9k_hw_chip_reset(struct ath_hw *ah,
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1112
				struct ath9k_channel *chan)
1113
{
1114
	if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1115 1116 1117
		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
			return false;
	} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
S
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1118
		return false;
1119

1120
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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1121
		return false;
1122

1123
	ah->chip_fullsleep = false;
S
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1124 1125
	ath9k_hw_init_pll(ah, chan);
	ath9k_hw_set_rfmode(ah, chan);
1126

S
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1127
	return true;
1128 1129
}

1130
static bool ath9k_hw_channel_change(struct ath_hw *ah,
L
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1131
				    struct ath9k_channel *chan)
1132
{
1133
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1134
	struct ath_common *common = ath9k_hw_common(ah);
1135
	struct ieee80211_channel *channel = chan->chan;
1136
	u32 qnum;
1137
	int r;
1138 1139 1140

	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
		if (ath9k_hw_numtxpending(ah, qnum)) {
1141 1142 1143
			ath_print(common, ATH_DBG_QUEUE,
				  "Transmit frames pending on "
				  "queue %d\n", qnum);
1144 1145 1146 1147
			return false;
		}
	}

1148
	if (!ath9k_hw_rfbus_req(ah)) {
1149 1150
		ath_print(common, ATH_DBG_FATAL,
			  "Could not kill baseband RX\n");
1151 1152 1153
		return false;
	}

1154
	ath9k_hw_set_channel_regs(ah, chan);
1155

1156
	r = ath9k_hw_rf_set_freq(ah, chan);
1157 1158 1159 1160
	if (r) {
		ath_print(common, ATH_DBG_FATAL,
			  "Failed to set channel\n");
		return false;
1161
	}
1162
	ath9k_hw_set_clockrate(ah);
1163

1164
	ah->eep_ops->set_txpower(ah, chan,
1165
			     ath9k_regd_get_ctl(regulatory, chan),
S
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1166 1167 1168
			     channel->max_antenna_gain * 2,
			     channel->max_power * 2,
			     min((u32) MAX_RATE_POWER,
1169
			     (u32) regulatory->power_limit));
1170

1171
	ath9k_hw_rfbus_done(ah);
1172

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1173 1174 1175
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1176
	ath9k_hw_spur_mitigate_freq(ah, chan);
S
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1177 1178 1179 1180

	return true;
}

1181
bool ath9k_hw_check_alive(struct ath_hw *ah)
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1182
{
1183 1184 1185
	int count = 50;
	u32 reg;

1186
	if (AR_SREV_9285_12_OR_LATER(ah))
1187 1188 1189 1190
		return true;

	do {
		reg = REG_READ(ah, AR_OBS_BUS_1);
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1191

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
		if ((reg & 0x7E7FFFEF) == 0x00702400)
			continue;

		switch (reg & 0x7E000B00) {
		case 0x1E000000:
		case 0x52000B00:
		case 0x18000B00:
			continue;
		default:
			return true;
		}
	} while (count-- > 0);
J
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1204

1205
	return false;
J
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1206
}
1207
EXPORT_SYMBOL(ath9k_hw_check_alive);
J
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1208

1209
int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1210
		   struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1211
{
1212
	struct ath_common *common = ath9k_hw_common(ah);
1213
	u32 saveLedState;
1214
	struct ath9k_channel *curchan = ah->curchan;
1215 1216
	u32 saveDefAntenna;
	u32 macStaId1;
S
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1217
	u64 tsf = 0;
1218
	int i, r;
1219

1220 1221
	ah->txchainmask = common->tx_chainmask;
	ah->rxchainmask = common->rx_chainmask;
1222

1223 1224
	if (!ah->chip_fullsleep) {
		ath9k_hw_abortpcurecv(ah);
1225
		if (!ath9k_hw_stopdmarecv(ah)) {
1226 1227
			ath_print(common, ATH_DBG_XMIT,
				"Failed to stop receive dma\n");
1228 1229
			bChannelChange = false;
		}
1230 1231
	}

1232
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1233
		return -EIO;
1234

1235
	if (curchan && !ah->chip_fullsleep)
1236 1237
		ath9k_hw_getnf(ah, curchan);

1238 1239 1240 1241 1242 1243 1244 1245 1246 1247
	ah->caldata = caldata;
	if (caldata &&
	    (chan->channel != caldata->channel ||
	     (chan->channelFlags & ~CHANNEL_CW_INT) !=
	     (caldata->channelFlags & ~CHANNEL_CW_INT))) {
		/* Operating channel changed, reset channel calibration data */
		memset(caldata, 0, sizeof(*caldata));
		ath9k_init_nfcal_hist_buffer(ah, chan);
	}

1248
	if (bChannelChange &&
1249 1250 1251
	    (ah->chip_fullsleep != true) &&
	    (ah->curchan != NULL) &&
	    (chan->channel != ah->curchan->channel) &&
1252
	    ((chan->channelFlags & CHANNEL_ALL) ==
1253
	     (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1254
	    (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1255

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1256
		if (ath9k_hw_channel_change(ah, chan)) {
1257
			ath9k_hw_loadnf(ah, ah->curchan);
1258
			ath9k_hw_start_nfcal(ah, true);
1259 1260
			if (AR_SREV_9271(ah))
				ar9002_hw_load_ani_reg(ah, chan);
1261
			return 0;
1262 1263 1264 1265 1266 1267 1268 1269 1270
		}
	}

	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
	if (saveDefAntenna == 0)
		saveDefAntenna = 1;

	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;

S
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1271
	/* For chips on which RTC reset is done, save TSF before it gets cleared */
1272 1273
	if (AR_SREV_9100(ah) ||
	    (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
S
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1274 1275
		tsf = ath9k_hw_gettsf64(ah);

1276 1277 1278 1279 1280 1281
	saveLedState = REG_READ(ah, AR_CFG_LED) &
		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);

	ath9k_hw_mark_phy_inactive(ah);

1282
	/* Only required on the first reset */
1283 1284 1285 1286 1287 1288 1289
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_RADIO_RF_RST);
		udelay(50);
	}

1290
	if (!ath9k_hw_chip_reset(ah, chan)) {
1291
		ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1292
		return -EINVAL;
1293 1294
	}

1295
	/* Only required on the first reset */
1296 1297 1298 1299 1300 1301 1302 1303
	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
		ah->htc_reset_init = false;
		REG_WRITE(ah,
			  AR9271_RESET_POWER_DOWN_CONTROL,
			  AR9271_GATE_MAC_CTL);
		udelay(50);
	}

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1304
	/* Restore TSF */
1305
	if (tsf)
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1306 1307
		ath9k_hw_settsf64(ah, tsf);

1308
	if (AR_SREV_9280_20_OR_LATER(ah))
1309
		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1310

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1311 1312 1313
	if (!AR_SREV_9300_20_OR_LATER(ah))
		ar9002_hw_enable_async_fifo(ah);

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1314
	r = ath9k_hw_process_ini(ah, chan);
1315 1316
	if (r)
		return r;
1317

1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328
	/*
	 * Some AR91xx SoC devices frequently fail to accept TSF writes
	 * right after the chip reset. When that happens, write a new
	 * value after the initvals have been applied, with an offset
	 * based on measured time difference
	 */
	if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
		tsf += 1500;
		ath9k_hw_settsf64(ah, tsf);
	}

1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345
	/* Setup MFP options for CCMP */
	if (AR_SREV_9280_20_OR_LATER(ah)) {
		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
		 * frames when constructing CCMP AAD. */
		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
			      0xc7ff);
		ah->sw_mgmt_crypto = false;
	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
		/* Disable hardware crypto for management frames */
		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
		ah->sw_mgmt_crypto = true;
	} else
		ah->sw_mgmt_crypto = true;

1346 1347 1348
	if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
		ath9k_hw_set_delta_slope(ah, chan);

1349
	ath9k_hw_spur_mitigate_freq(ah, chan);
1350
	ah->eep_ops->set_board_values(ah, chan);
1351

1352 1353
	ath9k_hw_set_operating_mode(ah, ah->opmode);

S
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1354 1355
	ENABLE_REGWRITE_BUFFER(ah);

1356 1357
	REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
	REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1358 1359
		  | macStaId1
		  | AR_STA_ID1_RTS_USE_DEF
1360
		  | (ah->config.
1361
		     ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1362
		  | ah->sta_id1_defaults);
1363
	ath_hw_setbssidmask(common);
1364
	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1365
	ath9k_hw_write_associd(ah);
1366 1367 1368
	REG_WRITE(ah, AR_ISR, ~0);
	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);

S
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1369 1370
	REGWRITE_BUFFER_FLUSH(ah);

1371
	r = ath9k_hw_rf_set_freq(ah, chan);
1372 1373
	if (r)
		return r;
1374

1375 1376
	ath9k_hw_set_clockrate(ah);

S
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1377 1378
	ENABLE_REGWRITE_BUFFER(ah);

1379 1380 1381
	for (i = 0; i < AR_NUM_DCU; i++)
		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);

S
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1382 1383
	REGWRITE_BUFFER_FLUSH(ah);

1384 1385
	ah->intr_txqs = 0;
	for (i = 0; i < ah->caps.total_queues; i++)
1386 1387
		ath9k_hw_resettxqueue(ah, i);

1388
	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1389
	ath9k_hw_ani_cache_ini_regs(ah);
1390 1391
	ath9k_hw_init_qos(ah);

1392
	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1393
		ath9k_enable_rfkill(ah);
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1394

1395
	ath9k_hw_init_global_settings(ah);
1396

1397
	if (!AR_SREV_9300_20_OR_LATER(ah)) {
S
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1398
		ar9002_hw_update_async_fifo(ah);
1399
		ar9002_hw_enable_wep_aggregation(ah);
1400 1401
	}

1402 1403 1404 1405 1406 1407 1408
	REG_WRITE(ah, AR_STA_ID1,
		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);

	ath9k_hw_set_dma(ah);

	REG_WRITE(ah, AR_OBS, 8);

S
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1409
	if (ah->config.rx_intr_mitigation) {
1410 1411 1412 1413
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
	}

1414 1415 1416 1417 1418
	if (ah->config.tx_intr_mitigation) {
		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
	}

1419 1420
	ath9k_hw_init_bb(ah, chan);

1421
	if (!ath9k_hw_init_cal(ah, chan))
1422
		return -EIO;
1423

S
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1424
	ENABLE_REGWRITE_BUFFER(ah);
1425

1426
	ath9k_hw_restore_chainmask(ah);
1427 1428
	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);

S
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1429 1430
	REGWRITE_BUFFER_FLUSH(ah);

1431 1432 1433
	/*
	 * For big endian systems turn on swapping for descriptors
	 */
1434 1435 1436 1437
	if (AR_SREV_9100(ah)) {
		u32 mask;
		mask = REG_READ(ah, AR_CFG);
		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1438
			ath_print(common, ATH_DBG_RESET,
S
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1439
				"CFG Byte Swap Set 0x%x\n", mask);
1440 1441 1442 1443
		} else {
			mask =
				INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
			REG_WRITE(ah, AR_CFG, mask);
1444
			ath_print(common, ATH_DBG_RESET,
S
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1445
				"Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1446 1447
		}
	} else {
1448 1449 1450 1451 1452 1453 1454
		if (common->bus_ops->ath_bus_type == ATH_USB) {
			/* Configure AR9271 target WLAN */
			if (AR_SREV_9271(ah))
				REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
			else
				REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
		}
1455
#ifdef __BIG_ENDIAN
1456 1457
                else
			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1458 1459 1460
#endif
	}

1461
	if (ah->btcoex_hw.enabled)
1462 1463
		ath9k_hw_btcoex_enable(ah);

1464
	if (AR_SREV_9300_20_OR_LATER(ah))
1465
		ar9003_hw_bb_watchdog_config(ah);
1466

1467
	return 0;
1468
}
1469
EXPORT_SYMBOL(ath9k_hw_reset);
1470

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1471 1472 1473 1474
/******************************/
/* Power Management (Chipset) */
/******************************/

1475 1476 1477 1478
/*
 * Notify Power Mgt is disabled in self-generated frames.
 * If requested, force chip to sleep.
 */
1479
static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1480
{
S
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1481 1482
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
1483 1484 1485 1486
		/*
		 * Clear the RTC force wake bit to allow the
		 * mac to go to sleep.
		 */
S
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1487 1488
		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
1489
		if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
S
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1490
			REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1491

1492
		/* Shutdown chip. Active low */
1493
		if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
S
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1494 1495
			REG_CLR_BIT(ah, (AR_RTC_RESET),
				    AR_RTC_RESET_EN);
S
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1496
	}
1497 1498 1499 1500 1501

	/* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_WA,
			  ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1502 1503
}

1504 1505 1506 1507 1508
/*
 * Notify Power Management is enabled in self-generating
 * frames. If request, set power mode of chip to
 * auto/normal.  Duration in units of 128us (1/8 TU).
 */
1509
static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1510
{
S
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1511 1512
	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
	if (setChip) {
1513
		struct ath9k_hw_capabilities *pCap = &ah->caps;
1514

S
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1515
		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1516
			/* Set WakeOnInterrupt bit; clear ForceWake bit */
S
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1517 1518 1519
			REG_WRITE(ah, AR_RTC_FORCE_WAKE,
				  AR_RTC_FORCE_WAKE_ON_INT);
		} else {
1520 1521 1522 1523
			/*
			 * Clear the RTC force wake bit to allow the
			 * mac to go to sleep.
			 */
S
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1524 1525
			REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
1526 1527
		}
	}
1528 1529 1530 1531

	/* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
	if (AR_SREV_9300_20_OR_LATER(ah))
		REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1532 1533
}

1534
static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1535
{
S
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1536 1537
	u32 val;
	int i;
1538

1539 1540 1541 1542 1543 1544
	/* Set Bits 14 and 17 of AR_WA before powering on the chip. */
	if (AR_SREV_9300_20_OR_LATER(ah)) {
		REG_WRITE(ah, AR_WA, ah->WARegVal);
		udelay(10);
	}

S
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1545 1546 1547 1548 1549 1550 1551
	if (setChip) {
		if ((REG_READ(ah, AR_RTC_STATUS) &
		     AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
			if (ath9k_hw_set_reset_reg(ah,
					   ATH9K_RESET_POWER_ON) != true) {
				return false;
			}
1552 1553
			if (!AR_SREV_9300_20_OR_LATER(ah))
				ath9k_hw_init_pll(ah, NULL);
S
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1554 1555 1556 1557
		}
		if (AR_SREV_9100(ah))
			REG_SET_BIT(ah, AR_RTC_RESET,
				    AR_RTC_RESET_EN);
1558

S
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1559 1560 1561
		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
			    AR_RTC_FORCE_WAKE_EN);
		udelay(50);
1562

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1563 1564 1565 1566 1567 1568 1569
		for (i = POWER_UP_TIME / 50; i > 0; i--) {
			val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
			if (val == AR_RTC_STATUS_ON)
				break;
			udelay(50);
			REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
				    AR_RTC_FORCE_WAKE_EN);
1570
		}
S
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1571
		if (i == 0) {
1572 1573 1574
			ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
				  "Failed to wakeup in %uus\n",
				  POWER_UP_TIME / 20);
S
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1575
			return false;
1576 1577 1578
		}
	}

S
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1579
	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1580

S
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1581
	return true;
1582 1583
}

1584
bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1585
{
1586
	struct ath_common *common = ath9k_hw_common(ah);
1587
	int status = true, setChip = true;
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1588 1589 1590 1591 1592 1593 1594
	static const char *modes[] = {
		"AWAKE",
		"FULL-SLEEP",
		"NETWORK SLEEP",
		"UNDEFINED"
	};

1595 1596 1597
	if (ah->power_mode == mode)
		return status;

1598 1599
	ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
		  modes[ah->power_mode], modes[mode]);
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1600 1601 1602 1603 1604 1605 1606

	switch (mode) {
	case ATH9K_PM_AWAKE:
		status = ath9k_hw_set_power_awake(ah, setChip);
		break;
	case ATH9K_PM_FULL_SLEEP:
		ath9k_set_power_sleep(ah, setChip);
1607
		ah->chip_fullsleep = true;
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1608 1609 1610 1611
		break;
	case ATH9K_PM_NETWORK_SLEEP:
		ath9k_set_power_network_sleep(ah, setChip);
		break;
1612
	default:
1613 1614
		ath_print(common, ATH_DBG_FATAL,
			  "Unknown power mode %u\n", mode);
1615 1616
		return false;
	}
1617
	ah->power_mode = mode;
S
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1618 1619

	return status;
1620
}
1621
EXPORT_SYMBOL(ath9k_hw_setpower);
1622

S
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1623 1624 1625 1626
/*******************/
/* Beacon Handling */
/*******************/

1627
void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1628 1629 1630
{
	int flags = 0;

1631
	ah->beacon_interval = beacon_period;
1632

S
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1633 1634
	ENABLE_REGWRITE_BUFFER(ah);

1635
	switch (ah->opmode) {
1636 1637
	case NL80211_IFTYPE_STATION:
	case NL80211_IFTYPE_MONITOR:
1638 1639 1640 1641 1642
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
		REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
		flags |= AR_TBTT_TIMER_EN;
		break;
1643
	case NL80211_IFTYPE_ADHOC:
1644
	case NL80211_IFTYPE_MESH_POINT:
1645 1646 1647 1648
		REG_SET_BIT(ah, AR_TXCFG,
			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
		REG_WRITE(ah, AR_NEXT_NDP_TIMER,
			  TU_TO_USEC(next_beacon +
1649 1650
				     (ah->atim_window ? ah->
				      atim_window : 1)));
1651
		flags |= AR_NDP_TIMER_EN;
1652
	case NL80211_IFTYPE_AP:
1653 1654 1655
		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
			  TU_TO_USEC(next_beacon -
1656
				     ah->config.
1657
				     dma_beacon_response_time));
1658 1659
		REG_WRITE(ah, AR_NEXT_SWBA,
			  TU_TO_USEC(next_beacon -
1660
				     ah->config.
1661
				     sw_beacon_response_time));
1662 1663 1664
		flags |=
			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
		break;
1665
	default:
1666 1667 1668
		ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
			  "%s: unsupported opmode: %d\n",
			  __func__, ah->opmode);
1669 1670
		return;
		break;
1671 1672 1673 1674 1675 1676 1677
	}

	REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
	REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));

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1678 1679
	REGWRITE_BUFFER_FLUSH(ah);

1680 1681 1682 1683 1684 1685 1686
	beacon_period &= ~ATH9K_BEACON_ENA;
	if (beacon_period & ATH9K_BEACON_RESET_TSF) {
		ath9k_hw_reset_tsf(ah);
	}

	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
}
1687
EXPORT_SYMBOL(ath9k_hw_beaconinit);
1688

1689
void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
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1690
				    const struct ath9k_beacon_state *bs)
1691 1692
{
	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1693
	struct ath9k_hw_capabilities *pCap = &ah->caps;
1694
	struct ath_common *common = ath9k_hw_common(ah);
1695

S
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1696 1697
	ENABLE_REGWRITE_BUFFER(ah);

1698 1699 1700 1701 1702 1703 1704
	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));

	REG_WRITE(ah, AR_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
	REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
		  TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));

S
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1705 1706
	REGWRITE_BUFFER_FLUSH(ah);

1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723
	REG_RMW_FIELD(ah, AR_RSSI_THR,
		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);

	beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;

	if (bs->bs_sleepduration > beaconintval)
		beaconintval = bs->bs_sleepduration;

	dtimperiod = bs->bs_dtimperiod;
	if (bs->bs_sleepduration > dtimperiod)
		dtimperiod = bs->bs_sleepduration;

	if (beaconintval == dtimperiod)
		nextTbtt = bs->bs_nextdtim;
	else
		nextTbtt = bs->bs_nexttbtt;

1724 1725 1726 1727
	ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
	ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
	ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
	ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1728

S
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1729 1730
	ENABLE_REGWRITE_BUFFER(ah);

S
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1731 1732 1733
	REG_WRITE(ah, AR_NEXT_DTIM,
		  TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
	REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1734

S
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1735 1736 1737
	REG_WRITE(ah, AR_SLEEP1,
		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
		  | AR_SLEEP1_ASSUME_DTIM);
1738

S
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1739 1740 1741 1742
	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
	else
		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1743

S
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1744 1745
	REG_WRITE(ah, AR_SLEEP2,
		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1746

S
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1747 1748
	REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
	REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1749

S
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1750 1751
	REGWRITE_BUFFER_FLUSH(ah);

S
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1752 1753 1754
	REG_SET_BIT(ah, AR_TIMER_MODE,
		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
		    AR_DTIM_TIMER_EN);
1755

1756 1757
	/* TSF Out of Range Threshold */
	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1758
}
1759
EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1760

S
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1761 1762 1763 1764
/*******************/
/* HW Capabilities */
/*******************/

1765
int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1766
{
1767
	struct ath9k_hw_capabilities *pCap = &ah->caps;
1768
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1769
	struct ath_common *common = ath9k_hw_common(ah);
1770
	struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1771

S
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1772
	u16 capField = 0, eeval;
1773
	u8 ant_div_ctl1;
1774

S
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1775
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1776
	regulatory->current_rd = eeval;
1777

S
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1778
	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1779
	if (AR_SREV_9285_12_OR_LATER(ah))
1780
		eeval |= AR9285_RDEXT_DEFAULT;
1781
	regulatory->current_rd_ext = eeval;
1782

S
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1783
	capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
S
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1784

1785
	if (ah->opmode != NL80211_IFTYPE_AP &&
1786
	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1787 1788 1789 1790 1791
		if (regulatory->current_rd == 0x64 ||
		    regulatory->current_rd == 0x65)
			regulatory->current_rd += 5;
		else if (regulatory->current_rd == 0x41)
			regulatory->current_rd = 0x43;
1792 1793
		ath_print(common, ATH_DBG_REGULATORY,
			  "regdomain mapped to 0x%x\n", regulatory->current_rd);
S
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1794
	}
1795

S
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1796
	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1797 1798 1799 1800 1801 1802
	if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
		ath_print(common, ATH_DBG_FATAL,
			  "no band has been marked as supported in EEPROM.\n");
		return -EINVAL;
	}

1803 1804
	if (eeval & AR5416_OPFLAGS_11A)
		pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1805

1806 1807
	if (eeval & AR5416_OPFLAGS_11G)
		pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
S
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1808

S
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1809
	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1810 1811 1812 1813
	/*
	 * For AR9271 we will temporarilly uses the rx chainmax as read from
	 * the EEPROM.
	 */
1814
	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1815 1816 1817
	    !(eeval & AR5416_OPFLAGS_11A) &&
	    !(AR_SREV_9271(ah)))
		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1818 1819
		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
	else
1820
		/* Use rx_chainmask from EEPROM. */
1821
		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1822

1823
	ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1824

S
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1825 1826
	pCap->low_2ghz_chan = 2312;
	pCap->high_2ghz_chan = 2732;
1827

S
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1828 1829
	pCap->low_5ghz_chan = 4920;
	pCap->high_5ghz_chan = 6100;
1830

1831 1832
	common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;

1833
	if (ah->config.ht_enable)
S
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1834 1835 1836
		pCap->hw_caps |= ATH9K_HW_CAP_HT;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1837

S
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1838 1839 1840 1841 1842
	if (capField & AR_EEPROM_EEPCAP_MAXQCU)
		pCap->total_queues =
			MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
	else
		pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1843

S
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1844 1845 1846 1847 1848
	if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
		pCap->keycache_size =
			1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
	else
		pCap->keycache_size = AR_KEYTABLE_SIZE;
1849

1850 1851 1852 1853
	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
	else
		pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1854

1855 1856
	if (AR_SREV_9271(ah))
		pCap->num_gpio_pins = AR9271_NUM_GPIO;
S
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1857 1858
	else if (AR_DEVID_7010(ah))
		pCap->num_gpio_pins = AR7010_NUM_GPIO;
1859
	else if (AR_SREV_9285_12_OR_LATER(ah))
1860
		pCap->num_gpio_pins = AR9285_NUM_GPIO;
1861
	else if (AR_SREV_9280_20_OR_LATER(ah))
S
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1862 1863 1864
		pCap->num_gpio_pins = AR928X_NUM_GPIO;
	else
		pCap->num_gpio_pins = AR_NUM_GPIO;
1865

S
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1866 1867 1868 1869 1870
	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
		pCap->hw_caps |= ATH9K_HW_CAP_CST;
		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
	} else {
		pCap->rts_aggr_limit = (8 * 1024);
1871 1872
	}

S
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1873 1874
	pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;

1875
#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1876 1877 1878 1879 1880 1881
	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
		ah->rfkill_gpio =
			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
		ah->rfkill_polarity =
			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
S
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1882 1883

		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1884
	}
S
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1885
#endif
1886
	if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1887 1888 1889
		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
	else
		pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1890

1891
	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
S
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1892 1893 1894
		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
	else
		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1895

1896
	if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
S
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1897 1898 1899 1900 1901
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
			AR_EEPROM_EEREGCAP_EN_KK_U2 |
			AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1902
	} else {
S
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1903 1904 1905
		pCap->reg_cap =
			AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
			AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1906 1907
	}

1908 1909 1910 1911
	/* Advertise midband for AR5416 with FCC midband set in eeprom */
	if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
	    AR_SREV_5416(ah))
		pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
S
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1912 1913

	pCap->num_antcfg_5ghz =
S
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1914
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
S
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1915
	pCap->num_antcfg_2ghz =
S
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1916
		ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1917

1918
	if (AR_SREV_9280_20_OR_LATER(ah) &&
1919
	    ath9k_hw_btcoex_supported(ah)) {
1920 1921
		btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
		btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1922

1923
		if (AR_SREV_9285(ah)) {
1924 1925
			btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
			btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1926
		} else {
1927
			btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1928
		}
1929
	} else {
1930
		btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1931
	}
1932

1933
	if (AR_SREV_9300_20_OR_LATER(ah)) {
1934 1935
		pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
				 ATH9K_HW_CAP_FASTCLOCK;
1936 1937 1938
		pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
		pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
		pCap->rx_status_len = sizeof(struct ar9003_rxs);
1939
		pCap->tx_desc_len = sizeof(struct ar9003_txc);
1940
		pCap->txs_len = sizeof(struct ar9003_txs);
1941 1942
		if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
			pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1943 1944
	} else {
		pCap->tx_desc_len = sizeof(struct ath_desc);
1945 1946 1947 1948 1949
		if (AR_SREV_9280_20(ah) &&
		    ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
		      AR5416_EEP_MINOR_VER_16) ||
		     ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
			pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1950
	}
1951

1952 1953 1954
	if (AR_SREV_9300_20_OR_LATER(ah))
		pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;

1955
	if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1956 1957
		pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;

1958 1959 1960 1961 1962 1963 1964 1965
	if (AR_SREV_9285(ah))
		if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
			ant_div_ctl1 =
				ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
			if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
				pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
		}

1966
	return 0;
1967 1968
}

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1969 1970 1971
/****************************/
/* GPIO / RFKILL / Antennae */
/****************************/
1972

1973
static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
S
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1974 1975 1976 1977
					 u32 gpio, u32 type)
{
	int addr;
	u32 gpio_shift, tmp;
1978

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1979 1980 1981 1982 1983 1984
	if (gpio > 11)
		addr = AR_GPIO_OUTPUT_MUX3;
	else if (gpio > 5)
		addr = AR_GPIO_OUTPUT_MUX2;
	else
		addr = AR_GPIO_OUTPUT_MUX1;
1985

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1986
	gpio_shift = (gpio % 6) * 5;
1987

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1988 1989 1990 1991
	if (AR_SREV_9280_20_OR_LATER(ah)
	    || (addr != AR_GPIO_OUTPUT_MUX1)) {
		REG_RMW(ah, addr, (type << gpio_shift),
			(0x1f << gpio_shift));
1992
	} else {
S
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1993 1994 1995 1996 1997
		tmp = REG_READ(ah, addr);
		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
		tmp &= ~(0x1f << gpio_shift);
		tmp |= (type << gpio_shift);
		REG_WRITE(ah, addr, tmp);
1998 1999 2000
	}
}

2001
void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2002
{
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2003
	u32 gpio_shift;
2004

2005
	BUG_ON(gpio >= ah->caps.num_gpio_pins);
2006

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2007 2008 2009 2010 2011 2012 2013
	if (AR_DEVID_7010(ah)) {
		gpio_shift = gpio;
		REG_RMW(ah, AR7010_GPIO_OE,
			(AR7010_GPIO_OE_AS_INPUT << gpio_shift),
			(AR7010_GPIO_OE_MASK << gpio_shift));
		return;
	}
2014

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2015
	gpio_shift = gpio << 1;
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2016 2017 2018 2019
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
2020
}
2021
EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2022

2023
u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2024
{
2025 2026 2027
#define MS_REG_READ(x, y) \
	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))

2028
	if (gpio >= ah->caps.num_gpio_pins)
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2029
		return 0xffffffff;
2030

S
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2031 2032 2033 2034 2035
	if (AR_DEVID_7010(ah)) {
		u32 val;
		val = REG_READ(ah, AR7010_GPIO_IN);
		return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
	} else if (AR_SREV_9300_20_OR_LATER(ah))
2036 2037
		return MS_REG_READ(AR9300, gpio) != 0;
	else if (AR_SREV_9271(ah))
2038
		return MS_REG_READ(AR9271, gpio) != 0;
2039
	else if (AR_SREV_9287_11_OR_LATER(ah))
2040
		return MS_REG_READ(AR9287, gpio) != 0;
2041
	else if (AR_SREV_9285_12_OR_LATER(ah))
2042
		return MS_REG_READ(AR9285, gpio) != 0;
2043
	else if (AR_SREV_9280_20_OR_LATER(ah))
2044 2045 2046
		return MS_REG_READ(AR928X, gpio) != 0;
	else
		return MS_REG_READ(AR, gpio) != 0;
2047
}
2048
EXPORT_SYMBOL(ath9k_hw_gpio_get);
2049

2050
void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
S
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2051
			 u32 ah_signal_type)
2052
{
S
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2053
	u32 gpio_shift;
2054

S
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2055 2056 2057 2058 2059 2060 2061
	if (AR_DEVID_7010(ah)) {
		gpio_shift = gpio;
		REG_RMW(ah, AR7010_GPIO_OE,
			(AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
			(AR7010_GPIO_OE_MASK << gpio_shift));
		return;
	}
2062

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2063
	ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
S
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2064 2065 2066 2067 2068
	gpio_shift = 2 * gpio;
	REG_RMW(ah,
		AR_GPIO_OE_OUT,
		(AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
		(AR_GPIO_OE_OUT_DRV << gpio_shift));
2069
}
2070
EXPORT_SYMBOL(ath9k_hw_cfg_output);
2071

2072
void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2073
{
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2074 2075 2076 2077 2078 2079 2080
	if (AR_DEVID_7010(ah)) {
		val = val ? 0 : 1;
		REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
			AR_GPIO_BIT(gpio));
		return;
	}

2081 2082 2083
	if (AR_SREV_9271(ah))
		val = ~val;

S
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2084 2085
	REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
		AR_GPIO_BIT(gpio));
2086
}
2087
EXPORT_SYMBOL(ath9k_hw_set_gpio);
2088

2089
u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2090
{
S
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2091
	return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2092
}
2093
EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2094

2095
void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2096
{
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2097
	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2098
}
2099
EXPORT_SYMBOL(ath9k_hw_setantenna);
2100

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2101 2102 2103 2104
/*********************/
/* General Operation */
/*********************/

2105
u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2106
{
S
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2107 2108
	u32 bits = REG_READ(ah, AR_RX_FILTER);
	u32 phybits = REG_READ(ah, AR_PHY_ERR);
2109

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2110 2111 2112 2113
	if (phybits & AR_PHY_ERR_RADAR)
		bits |= ATH9K_RX_FILTER_PHYRADAR;
	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
		bits |= ATH9K_RX_FILTER_PHYERR;
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2114

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2115
	return bits;
2116
}
2117
EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2118

2119
void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2120
{
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2121
	u32 phybits;
2122

S
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2123 2124
	ENABLE_REGWRITE_BUFFER(ah);

S
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2125 2126
	REG_WRITE(ah, AR_RX_FILTER, bits);

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2127 2128 2129 2130 2131 2132
	phybits = 0;
	if (bits & ATH9K_RX_FILTER_PHYRADAR)
		phybits |= AR_PHY_ERR_RADAR;
	if (bits & ATH9K_RX_FILTER_PHYERR)
		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
	REG_WRITE(ah, AR_PHY_ERR, phybits);
2133

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2134 2135 2136 2137 2138 2139
	if (phybits)
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
	else
		REG_WRITE(ah, AR_RXCFG,
			  REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
S
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2140 2141

	REGWRITE_BUFFER_FLUSH(ah);
S
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2142
}
2143
EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2144

2145
bool ath9k_hw_phy_disable(struct ath_hw *ah)
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2146
{
2147 2148 2149 2150 2151
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
S
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2152
}
2153
EXPORT_SYMBOL(ath9k_hw_phy_disable);
2154

2155
bool ath9k_hw_disable(struct ath_hw *ah)
S
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2156
{
2157
	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
S
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2158
		return false;
2159

2160 2161 2162 2163 2164
	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
		return false;

	ath9k_hw_init_pll(ah, NULL);
	return true;
2165
}
2166
EXPORT_SYMBOL(ath9k_hw_disable);
2167

2168
void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2169
{
2170
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2171
	struct ath9k_channel *chan = ah->curchan;
2172
	struct ieee80211_channel *channel = chan->chan;
2173

2174
	regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2175

2176
	ah->eep_ops->set_txpower(ah, chan,
2177
				 ath9k_regd_get_ctl(regulatory, chan),
2178 2179 2180
				 channel->max_antenna_gain * 2,
				 channel->max_power * 2,
				 min((u32) MAX_RATE_POWER,
2181
				 (u32) regulatory->power_limit));
2182
}
2183
EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2184

2185
void ath9k_hw_setopmode(struct ath_hw *ah)
2186
{
2187
	ath9k_hw_set_operating_mode(ah, ah->opmode);
2188
}
2189
EXPORT_SYMBOL(ath9k_hw_setopmode);
2190

2191
void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2192
{
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2193 2194
	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2195
}
2196
EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2197

2198
void ath9k_hw_write_associd(struct ath_hw *ah)
2199
{
2200 2201 2202 2203 2204
	struct ath_common *common = ath9k_hw_common(ah);

	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2205
}
2206
EXPORT_SYMBOL(ath9k_hw_write_associd);
2207

2208 2209
#define ATH9K_MAX_TSF_READ 10

2210
u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2211
{
2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222
	u32 tsf_lower, tsf_upper1, tsf_upper2;
	int i;

	tsf_upper1 = REG_READ(ah, AR_TSF_U32);
	for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
		tsf_lower = REG_READ(ah, AR_TSF_L32);
		tsf_upper2 = REG_READ(ah, AR_TSF_U32);
		if (tsf_upper2 == tsf_upper1)
			break;
		tsf_upper1 = tsf_upper2;
	}
2223

2224
	WARN_ON( i == ATH9K_MAX_TSF_READ );
2225

2226
	return (((u64)tsf_upper1 << 32) | tsf_lower);
S
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2227
}
2228
EXPORT_SYMBOL(ath9k_hw_gettsf64);
2229

2230
void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2231 2232
{
	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
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Alina Friedrichsen 已提交
2233
	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2234
}
2235
EXPORT_SYMBOL(ath9k_hw_settsf64);
2236

2237
void ath9k_hw_reset_tsf(struct ath_hw *ah)
S
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2238
{
2239 2240
	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
			   AH_TSF_WRITE_TIMEOUT))
2241 2242
		ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
			  "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2243

S
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2244 2245
	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
}
2246
EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2247

S
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2248
void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
S
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2249 2250
{
	if (setting)
2251
		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
S
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2252
	else
2253
		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
S
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2254
}
2255
EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2256

L
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2257
void ath9k_hw_set11nmac2040(struct ath_hw *ah)
S
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2258
{
L
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2259
	struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
S
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2260 2261
	u32 macmode;

L
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2262
	if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
S
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2263 2264 2265
		macmode = AR_2040_JOINED_RX_CLEAR;
	else
		macmode = 0;
2266

S
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2267
	REG_WRITE(ah, AR_2040_MODE, macmode);
2268
}
2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314

/* HW Generic timers configuration */

static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
{
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
				AR_NDP2_TIMER_MODE, 0x0002},
	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
				AR_NDP2_TIMER_MODE, 0x0004},
	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
				AR_NDP2_TIMER_MODE, 0x0008},
	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
				AR_NDP2_TIMER_MODE, 0x0010},
	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
				AR_NDP2_TIMER_MODE, 0x0020},
	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
				AR_NDP2_TIMER_MODE, 0x0040},
	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
				AR_NDP2_TIMER_MODE, 0x0080}
};

/* HW generic timer primitives */

/* compute and clear index of rightmost 1 */
static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
{
	u32 b;

	b = *mask;
	b &= (0-b);
	*mask &= ~b;
	b *= debruijn32;
	b >>= 27;

	return timer_table->gen_timer_index[b];
}

2315
u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2316 2317 2318
{
	return REG_READ(ah, AR_TSF_L32);
}
2319
EXPORT_SYMBOL(ath9k_hw_gettsf32);
2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332

struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
					  void (*trigger)(void *),
					  void (*overflow)(void *),
					  void *arg,
					  u8 timer_index)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;

	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);

	if (timer == NULL) {
2333 2334 2335
		ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
			  "Failed to allocate memory"
			  "for hw timer[%d]\n", timer_index);
2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
		return NULL;
	}

	/* allocate a hardware generic timer slot */
	timer_table->timers[timer_index] = timer;
	timer->index = timer_index;
	timer->trigger = trigger;
	timer->overflow = overflow;
	timer->arg = arg;

	return timer;
}
2348
EXPORT_SYMBOL(ath_gen_timer_alloc);
2349

2350 2351 2352 2353
void ath9k_hw_gen_timer_start(struct ath_hw *ah,
			      struct ath_gen_timer *timer,
			      u32 timer_next,
			      u32 timer_period)
2354 2355 2356 2357 2358 2359 2360 2361 2362 2363
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	u32 tsf;

	BUG_ON(!timer_period);

	set_bit(timer->index, &timer_table->timer_mask.timer_bits);

	tsf = ath9k_hw_gettsf32(ah);

2364 2365 2366
	ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
		  "curent tsf %x period %x"
		  "timer_next %x\n", tsf, timer_period, timer_next);
2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389

	/*
	 * Pull timer_next forward if the current TSF already passed it
	 * because of software latency
	 */
	if (timer_next < tsf)
		timer_next = tsf + timer_period;

	/*
	 * Program generic timer registers
	 */
	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
		 timer_next);
	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
		  timer_period);
	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
		    gen_tmr_configuration[timer->index].mode_mask);

	/* Enable both trigger and thresh interrupt masks */
	REG_SET_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
}
2390
EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2391

2392
void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	if ((timer->index < AR_FIRST_NDP_TIMER) ||
		(timer->index >= ATH_MAX_GEN_TIMER)) {
		return;
	}

	/* Clear generic timer enable bits. */
	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
			gen_tmr_configuration[timer->index].mode_mask);

	/* Disable both trigger and thresh interrupt masks */
	REG_CLR_BIT(ah, AR_IMR_S5,
		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));

	clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
}
2412
EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2413 2414 2415 2416 2417 2418 2419 2420 2421

void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;

	/* free the hardware generic timer slot */
	timer_table->timers[timer->index] = NULL;
	kfree(timer);
}
2422
EXPORT_SYMBOL(ath_gen_timer_free);
2423 2424 2425 2426 2427 2428 2429 2430

/*
 * Generic Timer Interrupts handling
 */
void ath_gen_timer_isr(struct ath_hw *ah)
{
	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
	struct ath_gen_timer *timer;
2431
	struct ath_common *common = ath9k_hw_common(ah);
2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445
	u32 trigger_mask, thresh_mask, index;

	/* get hardware generic timer interrupt status */
	trigger_mask = ah->intr_gen_timer_trigger;
	thresh_mask = ah->intr_gen_timer_thresh;
	trigger_mask &= timer_table->timer_mask.val;
	thresh_mask &= timer_table->timer_mask.val;

	trigger_mask &= ~thresh_mask;

	while (thresh_mask) {
		index = rightmost_index(timer_table, &thresh_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
2446 2447
		ath_print(common, ATH_DBG_HWTIMER,
			  "TSF overflow for Gen timer %d\n", index);
2448 2449 2450 2451 2452 2453 2454
		timer->overflow(timer->arg);
	}

	while (trigger_mask) {
		index = rightmost_index(timer_table, &trigger_mask);
		timer = timer_table->timers[index];
		BUG_ON(!timer);
2455 2456
		ath_print(common, ATH_DBG_HWTIMER,
			  "Gen timer[%d] trigger\n", index);
2457 2458 2459
		timer->trigger(timer->arg);
	}
}
2460
EXPORT_SYMBOL(ath_gen_timer_isr);
2461

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/********/
/* HTC  */
/********/

void ath9k_hw_htc_resetinit(struct ath_hw *ah)
{
	ah->htc_reset_init = true;
}
EXPORT_SYMBOL(ath9k_hw_htc_resetinit);

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static struct {
	u32 version;
	const char * name;
} ath_mac_bb_names[] = {
	/* Devices with external radios */
	{ AR_SREV_VERSION_5416_PCI,	"5416" },
	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
	{ AR_SREV_VERSION_9100,		"9100" },
	{ AR_SREV_VERSION_9160,		"9160" },
	/* Single-chip solutions */
	{ AR_SREV_VERSION_9280,		"9280" },
	{ AR_SREV_VERSION_9285,		"9285" },
2484 2485
	{ AR_SREV_VERSION_9287,         "9287" },
	{ AR_SREV_VERSION_9271,         "9271" },
2486
	{ AR_SREV_VERSION_9300,         "9300" },
2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503
};

/* For devices with external radios */
static struct {
	u16 version;
	const char * name;
} ath_rf_names[] = {
	{ 0,				"5133" },
	{ AR_RAD5133_SREV_MAJOR,	"5133" },
	{ AR_RAD5122_SREV_MAJOR,	"5122" },
	{ AR_RAD2133_SREV_MAJOR,	"2133" },
	{ AR_RAD2122_SREV_MAJOR,	"2122" }
};

/*
 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
 */
2504
static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
		if (ath_mac_bb_names[i].version == mac_bb_version) {
			return ath_mac_bb_names[i].name;
		}
	}

	return "????";
}

/*
 * Return the RF name. "????" is returned if the RF is unknown.
 * Used for devices with external radios.
 */
2521
static const char *ath9k_hw_rf_name(u16 rf_version)
2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532
{
	int i;

	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
		if (ath_rf_names[i].version == rf_version) {
			return ath_rf_names[i].name;
		}
	}

	return "????";
}
2533 2534 2535 2536 2537 2538

void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
{
	int used;

	/* chipsets >= AR9280 are single-chip */
2539
	if (AR_SREV_9280_20_OR_LATER(ah)) {
2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557
		used = snprintf(hw_name, len,
			       "Atheros AR%s Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev);
	}
	else {
		used = snprintf(hw_name, len,
			       "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
			       ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
			       ah->hw_version.macRev,
			       ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
						AR_RADIO_SREV_MAJOR)),
			       ah->hw_version.phyRev);
	}

	hw_name[used] = '\0';
}
EXPORT_SYMBOL(ath9k_hw_name);