- 21 3月, 2006 11 次提交
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由 Michael Chan 提交于
Support one-shot MSI on 5787. This one-shot MSI idea is credited to David Miller. In this mode, MSI disables itself automatically after it is generated, saving the driver a register access to disable it for NAPI. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Support ipv6 tx csum on 5787 by setting NETIF_F_HW_CSUM. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Support 5787 hardware TSO using a new flag TG3_FLG2_HW_TSO_2. Since the TSO interface is slightly different and these chips have finally fixed the 4GB DMA problem and do not have the 40-bit DMA problem, a new hard_start_xmit is used for these chips. All previous chips will use the old hard_start_xmit that is now renamed tg3_start_xmit_dma_bug(). Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Support additional nvrams and new nvram format for 5787 and 5754. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Add basic support for 2 new chips 5787 and 5754. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Fix-up tg3_get_ringparam() to return the correct parameters. Set the jumbo rx ring parameter only if it is supported by the chip and currently in use. Add missing value for tx_max_pending, noticed by Rick Jones. Update version to 3.51. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Add missing netif_running() checks in tg3's dev->set_multicast_list() and dev->set_mac_address(). If not netif_running(), these 2 calls can simply return 0 after storing the new settings if required. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Update version to 3.50. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Support WoL during shutdown by calling tg3_set_power_state(tp, PCI_D3hot) during tg3_close(). Change the power state parameter to pci_power_t type and use constants defined in pci.h. Certain ethtool operations cannot be performed after tg3_close() because the device will go to low power state. Add return -EAGAIN in such cases where appropriate. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Enable TSO by default on newer chips that support TSO in hardware. Leave TSO off by default on older chips that do firmware TSO because performance is slightly lower. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Add support for 5714S and 5715S. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 3月, 2006 2 次提交
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由 David S. Miller 提交于
Sun does't put an SEEPROM behind the tigon3 chip, among other things, so accesses to these areas just give bus timeouts. Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
The 40-bit DMA workaround recently implemented for 5714, 5715, and 5780 needs to be expanded because there may be other tg3 devices behind the EPB Express to PCIX bridge in the 5780 class device. For example, some 4-port card or mother board designs have 5704 behind the 5714. All devices behind the EPB require the 40-bit DMA workaround. Thanks to Chris Elmquist again for reporting the problem and testing the patch. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 12 3月, 2006 1 次提交
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由 Adrian Bunk 提交于
The Coverity checker spotted this dead code (note that (clock_ctrl == 7) is already handled above). Signed-off-by: NAdrian Bunk <bunk@stusta.de> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 07 3月, 2006 1 次提交
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由 Michael Chan 提交于
Add DMA workaround for chips that do not support full 64-bit DMA addresses. 5714, 5715, and 5780 chips only support DMA addresses less than 40 bits. On 64-bit systems with IOMMU, set the dma_mask to 40-bit so that pci_map_xxx() calls will map the DMA address below 40 bits if necessary. On 64-bit systems without IOMMU, set the dma_mask to 64-bit and check for DMA addresses exceeding the limit in tg3_start_xmit(). 5788 only supports 32-bit DMA so need to set the mask appropriately also. Thanks to Chris Elmquist at SGI for reporting and helping to debug the problem on 5714. Thanks to David Miller for explaining the HIGHMEM and DMA stuff. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 3月, 2006 1 次提交
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由 Arjan van de Ven 提交于
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- 28 2月, 2006 1 次提交
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由 David S. Miller 提交于
Some Sun parts don't have PCI_VENDOR_ID_SUN in the subsystem vendor ID. So add another fallback test, which is the name of the OBP firmware device tree node. If it's a Sun part we'll get "network", else it will be named "ethernet". Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 03 2月, 2006 2 次提交
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由 David S. Miller 提交于
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Make sure tg3_reset_task() is flushed in the close and suspend paths as noted by Jeff Garzik. In the close path, calling flush_scheduled_work() may cause deadlock if linkwatch_event() is on the workqueue. linkwatch_event() will try to get the rtnl_lock() which is already held by tg3_close(). So instead, we set a flag in tg3_reset_task() and tg3_close() polls the flag until it is cleared. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 17 1月, 2006 1 次提交
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由 Michael Chan 提交于
Add nvram lock count so that calls to tg3_nvram_lock()/unlock() can be nested. Add error checking to all callers of tg3_nvram_lock() where appropriate. To prevent nvram lock failures after halting the firmware, it is also necessary to release firmware's nvram lock in tg3_halt_cpu(). Update version to 3.48. Based on David Miller's initial patch. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 1月, 2006 2 次提交
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由 Alexey Dobriyan 提交于
Turning struct iphdr::tot_len into __be16 added sparse warning. Signed-off-by: NAlexey Dobriyan <adobriyan@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Arnaldo Carvalho de Melo 提交于
To help in reducing the number of include dependencies, several files were touched as they were getting needed headers indirectly for stuff they use. Thanks also to Alan Menegotto for pointing out that net/dccp/proto.c had linux/dccp.h include twice. Signed-off-by: NArnaldo Carvalho de Melo <acme@mandriva.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 12月, 2005 2 次提交
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由 David S. Miller 提交于
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Chris Elmquist 提交于
Resubmitting after recommendation to use GET_REG32_1() instead of GET_REG32_LOOP(..., 1). Retested. Problem remains fixed. Prevent tg3_get_regs() from reading reserved and undocumented registers at RX_CPU_BASE and TX_CPU_BASE offsets which caused hostile behavior on PCIe platforms. Acked-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 12月, 2005 4 次提交
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由 Michael Chan 提交于
Skip the memory 0xb50 to 0x1000 during "ethtool -t" memory test. Overwriting memory in this region can cause ASF problems. Update version and release date. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
The tw32_f() function (register write with immediate read flush) can hang when used on some registers to switch clock frequencies and power. A new tw32_wait_f() is added for such registers with the delay before the read and after the read. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Add some missing workarounds in tg3_set_power_state(): 1. Workaround to prevent overdrawing current on 5714. 2. Do not power down 5700's PHY because of hw limitation. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Locate the pdev_peer for dual port 5714 NIC devices in addition to 5704 devices. The name is also changed to tg3_find_peer() from tg3_find_5704_peer(). It is also necessary to call netdev_priv() to get to the peer's private tg3 structure. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 12月, 2005 4 次提交
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由 Michael Chan 提交于
Fix the following bugs in tg3_set_power_state(): 1. Both WOL and ASF flags require switching to aux power. 2. Add a missing handshake with firmware to enable WOL. 3. Turn off the PHY if both WOL and ASF are disabled. 4. Add nvram arbitration before halting the firmware. 5. Fix tg3_setup_copper_phy() to switch to 100Mbps when changing to low power state. Update revision and date. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
If the dual-port 5704 is configured as a single-port device with only one PCI function, it would trigger a BUG() condition in tg3_find_5704_peer(). This fixes the problem by returning its own pdev if the peer cannot be found. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Fix tg3_suspend() and tg3_resume() by clearing and setting the TG3_FLAG_INIT_COMPLETE flag when appropriate. tg3_set_power_state() looks at TG3_FLAG_INIT_COMPLETE on the peer device to determine when to appropriately switch to aux power. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
The nvram arbitration rules were not strictly followed in a few places and this could lead to reading corrupted values from the nvram. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 07 12月, 2005 1 次提交
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由 Stephen Hemminger 提交于
[ Move assosciated code comment to the correct spot, and update driver version and release date -DaveM ] Signed-off-by: NStephen Hemminger <shemminger@osdl.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 30 10月, 2005 1 次提交
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由 Tobias Klauser 提交于
This one from my DMA_{32,64}BIT_MASK series did not seem to make it through to upstream. Use the DMA_{32,64}BIT_MASK constants from dma-mapping.h when calling pci_set_dma_mask() or pci_set_consistent_dma_mask() This patch includes dma-mapping.h explicitly because it caused errors on some architectures otherwise. See http://marc.theaimsgroup.com/?t=108001993000001&r=1&w=2 for details Signed-off-by: NTobias Klauser <tklauser@nuerscht.ch> Signed-off-by: NJeff Garzik <jgarzik@pobox.com>
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- 29 10月, 2005 4 次提交
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由 Jesper Juhl 提交于
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由 Michael Chan 提交于
Update version and reldate and add more sanity checking to tg3_set_settings(). Signed-off-by: NGary Zambrano <zambrano@broadcom.com> Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NJeff Garzik <jgarzik@pobox.com>
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由 Michael Chan 提交于
Change the ASF heart beat to 5 seconds for faster detection of system crash. The driver sends the heartbeat every 2 seconds and the ASF firmware will timeout and reset the device if no heartbeat is received after 5 seconds. The old scheme of 2 minutes is ineffective. tg3_write_mem_fast() is added to speed up the IO to send the heartbeat. When no workaround is needed, it will use direct MMIO to memory space to write to memory. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NJeff Garzik <jgarzik@pobox.com>
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由 Michael Chan 提交于
Add complete support for 5714/5715. These chips are very similar to 5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is added to identify these chips. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NJeff Garzik <jgarzik@pobox.com>
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- 04 10月, 2005 2 次提交
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由 David S. Miller 提交于
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Michael Chan 提交于
Test for VIA K8T800 north bridge instead of AMD K8 HyperTransport bridge based on new information from Andi Kleen. The AMD HyperTransport interface is not responsible for PCI transactions and so the re-ordering is more likely done by the VIA north bridge. This code is subject to change if we get more information from AMD or VIA. PCI Express devices are excluded from doing the read flush since all chipsets in the write_reorder list are PCI chipsets. Signed-off-by: NMichael Chan <mchan@broadcom.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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