pp->io_base, which is the input of the outbound IO address translation
unit, should be the CPU address.  It was incorrectly programmed to the
realio address.

We should pass global_io_offset rather than sys->io_offset to
pci_ioremap_io(), so we map the new window into the first available spot in
the Linux view of the I/O space.

We must also pass CPU address instead of realio address to pci_ioremap_io().

This patch fixes above issue.  It has been tested with Lecroy PTC in AIC
mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Tested-by: NMohit Kumar <mohit.kumar@st.com>
Tested-by: NTim Harvey <tharvey@gateworks.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marek Vasut <marex@denx.de
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>

The cfg_read/write functions are DesignWare-specific.  Add dw_pcie prefix
to avoid collision in global name space.
Tested-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

The interrupts were cleared after the IRQ handler was called.  This means
that new interrupts that occur after the handler handled the previous IRQ
but before the interrupt is cleared will be missed.
Tested-by: NMarek Vasut <marex@denx.de>
Tested-by: NMatthias Mann <m.mann@arkona-technologies.de>
Signed-off-by: NHarro Haan <hrhaan@gmail.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NMohit Kumar <mohit.kumar@st.com>
Cc: Richard Zhu <hong-xing.zhu@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Juergen Beisert <jbe@pengutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Sean Cross <xobs@kosagi.com>

It's conventional to use "for" rather than "while" for simple iteration.
No functional change.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

write_msi_msg() does exactly the same so there is no need to explicitly
call pci_write_config_word() and do the same twice.
Tested-by: NMohit Kumar <mohit.kumar@st.com>
Signed-off-by: NBjørn Erik Nilsen <ben@datarespons.no>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NJingoo Han <jg1.han@samsung.com>

904d0e78 ("PCI: designware: Add irq_create_mapping()") resulted in
pre-allocated irq descs.  Problem was that in assign_irq() these descs were
explicitly allocated and hence also freed, resulting in a crash.  We also
need to clear the entire irq range in teardown.  With this commit the
teardown basically does exactly the opposite of what was done in setup.

The crash this fixes looks like:

  Unable to handle kernel NULL pointer dereference at virtual address 00000020
  PC is at dw_msi_teardown_irq+0x40/0x118
  LR is at trace_hardirqs_on_caller+0xf4/0x1c0
  Backtrace:
  [<802c401c>] (dw_msi_teardown_irq+0x0/0x118) from [<802c1844>] (arch_teardown_msi_irq+0x3c/0x40)
  [<802c1808>] (arch_teardown_msi_irq+0x0/0x40) from [<802c1a08>] (default_teardown_msi_irqs+0x68/0x84)
  [<802c19a0>] (default_teardown_msi_irqs+0x0/0x84) from [<802c1a34>] (arch_teardown_msi_irqs+0x10/0x14)
  [<802c1a24>] (arch_teardown_msi_irqs+0x0/0x14) from [<802c1ad0>] (free_msi_irqs+0x98/0x144)
  [<802c1a38>] (free_msi_irqs+0x0/0x144) from [<802c2570>] (pci_disable_msi+0x48/0x60)
  [<802c2528>] (pci_disable_msi+0x0/0x60) from [<7f0057d4>] (sxdma_irq_free+0x44/0x48 [sxdma])

[bhelgaas: add crash info]
Tested-by: NMohit Kumar <mohit.kumar@st.com>
Signed-off-by: NBjørn Erik Nilsen <ben@datarespons.no>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NJingoo Han <jg1.han@samsung.com>

Fix whitespace, capitalization, and spelling errors.  No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.

Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus())
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Without irq_create_mapping(), the correct IRQ number cannot be
provided.  In this case, it makes problems such as NULL dereference.
Thus, irq_create_mapping() should be added for MSI.
Suggested-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NPratyush Anand <pratyush.anand@st.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

The following variables and functions are used only in pcie-designware.c,
so make them static:

  global_io_offset
  dw_pcie_rd_own_conf()
  dw_pcie_wr_own_conf()
  dw_pcie_setup()
  dw_pcie_scan_bus()
  dw_pcie_map_irq()
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

This patch adds support for Message Signaled Interrupt in the
Exynos PCIe driver using Synopsys designware PCIe core IP.
Signed-off-by: NSiva Reddy Kallam <siva.kallam@samsung.com>
Signed-off-by: NSrikanth T Shivanand <ts.srikanth@samsung.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>

The "dbi_addr" argument to dw_pcie_readl_rc() and dw_pcie_writel_rc()
is redundant and misleading because we always have the "struct pcie_port"
and we always want to use the address from there.

This patch removes the argument and changes the callers to match.
No functional change.

[bhelgaas: changelog]
Signed-off-by: NSeungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NJingoo Han <jg1.han@samsung.com>

Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.

Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>

Exynos5440 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.
Signed-off-by: NSurendranath Gurivireddy Balla <suren.reddy@samsung.com>
Signed-off-by: NSiva Reddy Kallam <siva.kallam@samsung.com>
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>