1. 10 9月, 2006 1 次提交
  2. 04 9月, 2006 1 次提交
  3. 02 9月, 2006 1 次提交
  4. 31 8月, 2006 2 次提交
  5. 30 8月, 2006 12 次提交
  6. 25 8月, 2006 4 次提交
  7. 24 8月, 2006 1 次提交
    • A
      [POWERPC] hugepage BUG fix · c9169f87
      Adam Litke 提交于
      On Tue, 2006-08-15 at 08:22 -0700, Dave Hansen wrote:
      > kernel BUG in cache_free_debugcheck at mm/slab.c:2748!
      
      Alright, this one is only triggered when slab debugging is enabled.  The
      slabs are assumed to be aligned on a HUGEPTE_TABLE_SIZE boundary.  The free
      path makes use of this assumption and uses the lowest nibble to pass around
      an index into an array of kmem_cache pointers.  With slab debugging turned
      on, the slab is still aligned, but the "working" object pointer is not.
      This would break the assumption above that a full nibble is available for
      the PGF_CACHENUM_MASK.
      
      The following patch reduces PGF_CACHENUM_MASK to cover only the two least
      significant bits, which is enough to cover the current number of 4 pgtable
      cache types.  Then use this constant to mask out the appropriate part of
      the huge pte pointer.
      Signed-off-by: NAdam Litke <agl@us.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      c9169f87
  8. 23 8月, 2006 11 次提交
  9. 18 8月, 2006 5 次提交
  10. 17 8月, 2006 2 次提交
    • B
      [POWERPC] Fix irq radix tree remapping typo · e5c14ce1
      Benjamin Herrenschmidt 提交于
      The code for using the radix tree for reverse mapping of interrupts has
      a typo that causes it to create incorrect mappings if the software and
      hardware numbers happen to be different. This would, among others, cause
      the IDE interrupt to fail on js20's. This fixes it.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      e5c14ce1
    • A
      [POWERPC] kprobes: Fix possible system crash during out-of-line single-stepping · 83db3dde
      Ananth N Mavinakayanahalli 提交于
      - On archs that have no-exec support, we vmalloc() a executable scratch
      area of PAGE_SIZE and divide it up into an array of slots of maximum
      instruction size for that arch
      - On a kprobe registration, the original instruction is copied to the
      first available free slot, so if multiple kprobes are registered, chances
      are, they get contiguous slots
      - On POWER4, due to not having coherent icaches, we could hit a situation
      where a probe that is registered on one processor, is hit immediately on
      another. This second processor could have fetched the stream of text from
      the out-of-line single-stepping area *before* the probe registration
      completed, possibly due to an earlier (and a different) kprobe hit and
      hence would see stale data at the slot.
      
      Executing such an arbitrary instruction lead to a problem as reported
      in LTC bugzilla 23555.
      
      The correct solution is to call flush_icache_range() as soon as the
      instruction is copied for out-of-line single-stepping, so the correct
      instruction is seen on all processors.
      
      Thanks to Will Schmidt who tracked this down.
      Signed-off-by: NAnanth N Mavinakayanahalli <ananth@in.ibm.com>
      Acked-by: NWill Schmidt <will_schmidt@vnet.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      83db3dde