Update main clk documentation to match main clk implementation rework.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NWolfram Sang <wsa@sang-engineering.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

MOXA ART SoCs allow to determine PLL output and APB frequencies
by reading registers holding multiplier and divisor information.

Add a clock driver for this SoC.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The Core Divider clock support two new compatible strings for Armada
375 and Armada 380 SoCs. Add the compatible strings to the documentation.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This patch adds support for the new v2 version of the axi-clkgen core.
Unfortunately the method of accessing the registers is quite different on v2,
while the content still stays largely the same. So the patch adds a small
abstraction layer which implements the specific read and write functions for v1
and v2 in callback functions.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>

Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch replaces magic numbers with macros defined in DT header
in exynos5440 clock bindings.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The patch replaces magic numbers with macros defined in DT header
in exynos5420 clock bindings.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The patch replaces magic numbers with macros defined in DT header
in exynos5250 clock bindings.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The patch replaces magic numbers with macros defined in DT header
in exynos4 clock bindings.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The DT bindings document a renesas,indices property, while the code, the
DT example and the DT sources all use renesas,clock-indices. Fix the
documentation.

The shmobile mstp DT bindings have been merged in v3.14-rc1 with a bug
in the DT ABI, a fix during the -rc series is appropriate.
Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: NSimon Horman <horms@verge.net.au>

Add a property called clock-indices to allow clock-output-names
to be used where the index used to lookup a clock is not a 1:1
mapping to the array position in the clock-output-names
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
    prepare function to the gate clk that will toggle clock phase setting.
    Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
    set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
    loaded after the clock driver.
v2: Use the syscon driver

The Allwinner A10 compatibles were following a slightly different compatible
patterns than the rest of the SoCs for historical reasons. Add compatibles
matching the other pattern to the clock driver for consistency, and keep the
older one for backward compatibility.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>

The Allwinner A20/A31 clock module controls the transmit clock source
and interface type of the GMAC ethernet controller. Model this as
a single clock for GMAC drivers to use.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>

The A31 has a slightly different PLL6 clock. Add support for this new clock in
our driver.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>

Add register definitions for the usb-clk register found on sun4i, sun5i and
sun7i SoCs.
Signed-off-by: NRoman Byshko <rbyshko@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>

Add the binding information for the gating clocks of the Armada 380
SoCs and the Armada 385 SoCs.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Add the binding information for the core clocks of the Armada 380 and
Armada 385 SoCs
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Add the binding information for the gating clocks of the Armada 375 SoCs
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Add the binding information for the core clocks of the Armada 375 SoCs
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This atomic commit changes the Integrator clock implementation
and the machines to register clocks from the device tree and
use these instead of the previous hard-coded clocks.

In the clock implementation all hard-coded clocks and the
special initialization function call goes away, and is
replaced by two compatible strings for the two clocks
available on the core module.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

clock-output-names is now required for most of sunxi clock nodes, to
provide the name of the corresponding clock. Add the new requirements,
exceptions, as well as examples.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NEmilio López <emilio@elopez.com.ar>

Adds the clock bindings for Freescale PowerPC CoreNet platforms
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
[scottwood@freescale.com: fixed clock-frequency in example]
Signed-off-by: NScott Wood <scottwood@freescale.com>

OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.

APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

ti,mux-clock provides now a binding for basic mux support. This is just
using the basic clock type.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Some OMAP clocks require knowledge about their parent clockdomain for
book keeping purposes. This patch creates a new DT binding for TI
clockdomains, which act as a collection of device clocks. Clockdomain
itself is rather misleading name for the hardware functionality, as at
least on OMAP4 / OMAP5 / DRA7 the clockdomains can be collections of either
clocks and/or IP blocks, thus idle-domain or such might be more appropriate.
For most cases on these SoCs, the kernel doesn't even need the information
and the mappings can be ignored.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds support for TI specific gate clocks. These behave as basic
gate-clock, but have different ops / hw-ops for controlling the actual
gate, for example waiting until the clock is ready. Several sub-types
are supported:
- ti,gate-clock: basic gate clock with default ops/hwops
- ti,clkdm-gate-clock: clockdomain level gate control
- ti,dss-gate-clock: gate clock with DSS specific hardware handling
- ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling
- ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This behaves exactly in similar manner to basic fixed-factor-clock, but
adds a few properties on top for handling clock hardware autoidling.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds support for TI divider clock binding, which simply uses
the basic clock divider to provide the features needed.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This is a multipurpose clock node, which contains support for multiple
sub-clocks. Uses basic composite clock type to implement the actual
functionality, and TI specific gate, mux and divider clocks.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

fix a typo in the "clock specifiers" discussion,
clarify that clock specifiers (the integer cells
part that goes with the phandle) may be empty

Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: devicetree@vger.kernel.org
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NGerhard Sittig <gsi@denx.de>
Signed-off-by: NRob Herring <robh@kernel.org>