1. 23 2月, 2010 2 次提交
    • J
      drm/i915: add dynamic performance control support for Ironlake · f97108d1
      Jesse Barnes 提交于
      Ironlake (and 965GM, which this patch doesn't support) supports a
      hardware performance and power management feature that allows it to
      adjust to changes in GPU load over time with software help.  The goal
      if this is to maximize performance/power for a given workload.
      
      This patch enables that feature, which is also a requirement for
      supporting Intelligent Power Sharing, a feature which allows for
      dynamic budgeting of power between the CPU and GPU in Arrandale
      platforms.
      Tested-by: Nykzhao <yakui.zhao@intel.com>
      [anholt: Resolved against the irq handler loop removal]
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: NEric Anholt <eric@anholt.net>
      f97108d1
    • L
      drm/i915: enable memory self refresh on 9xx · ee980b80
      Li Peng 提交于
      Enabling memory self refresh (SR) on 9xx needs to set additional
      register bits. On 945, we need bit 31 of FW_BLC_SELF to enable the
      write to self refresh bit and bit 16 to enable the write of self
      refresh watermark. On 915, bit 12 of INSTPM is used to enable SR.
      
      SR will take effect when CPU enters C3+ state and its entry/exit
      should be automatically controlled by H/W, driver only needs to set
      SR enable bits in wm update. But this isn't safe in my test on 945
      because GPU is hung. So this patch explicitly enables SR when GPU
      is idle, and disables SR when it is busy. In my test on a netbook of
      945GSE chipset, it saves about 0.8W idle power.
      Signed-off-by: NLi Peng <peng.li@intel.com>
      [anholt: rebased against 33c5fd12
      by adding disable of INSTPM SR bit on 915GM for two pipe setup]
      Signed-off-by: NEric Anholt <eric@anholt.net>
      ee980b80
  2. 17 2月, 2010 3 次提交
  3. 13 2月, 2010 8 次提交
  4. 12 2月, 2010 26 次提交
  5. 11 2月, 2010 1 次提交