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  1. 05 1月, 2012 1 次提交
  3. 21 11月, 2011 1 次提交
  5. 17 10月, 2011 3 次提交
  7. 24 6月, 2011 2 次提交
  9. 12 5月, 2011 1 次提交
  11. 31 3月, 2011 1 次提交
  13. 03 2月, 2011 1 次提交
  15. 03 1月, 2011 1 次提交
    • A
      ARM: 6605/1: Add missing include "asm/memory.h" · 7c0ab43e
      由 Axel Lin 提交于 
      This patch fixes below build error by adding the missing asm/memory.h,
which is needed for arch_is_coherent().

$ make pxa3xx_defconfig; make
  CC      init/do_mounts_rd.o
In file included from include/linux/list_bl.h:5,
                 from include/linux/rculist_bl.h:7,
                 from include/linux/dcache.h:7,
                 from include/linux/fs.h:381,
                 from init/do_mounts_rd.c:3:
include/linux/bit_spinlock.h: In function 'bit_spin_unlock':
include/linux/bit_spinlock.h:61: error: implicit declaration of function 'arch_is_coherent'
make[1]: *** [init/do_mounts_rd.o] Error 1
make: *** [init] Error 2
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Acked-by: NPeter Huewe <peterhuewe@gmx.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7c0ab43e
  17. 24 12月, 2010 1 次提交
  19. 20 11月, 2010 1 次提交
  21. 08 10月, 2010 1 次提交
  23. 08 9月, 2010 1 次提交
  25. 27 7月, 2010 1 次提交
  27. 17 5月, 2010 1 次提交
  29. 26 3月, 2010 1 次提交
    • C
      ARM: 5996/1: ARM: Change the mandatory barriers implementation (4/4) · e7c5650f
      由 Catalin Marinas 提交于 
      The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor
systems for things like ordering Normal Non-cacheable memory accesses
with DMA transfer (via Device memory writes). The current implementation
uses dmb() for mb() and friends but this is not sufficient. The DMB only
ensures the relative ordering of the observability of accesses by other
processors or devices acting as masters. In case of DMA transfers
started by writes to device memory, the relative ordering is not ensured
because accesses to slave ports of a device are not considered
observable by the DMB definition.

A DSB is required for the data to reach the main memory (even if mapped
as Normal Non-cacheable) before the device receives the notification to
begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or
PL310) buffer stores to Normal Non-cacheable memory and this would need
to be drained with the outer_sync() function call.

The patch also allows platforms to define their own mandatory barriers
implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a
mach/barriers.h file.

Note that the SMP barriers are unchanged (being DMBs as before) since
they are only guaranteed to work with Normal Cacheable memory.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      e7c5650f
  31. 16 2月, 2010 1 次提交
  33. 25 11月, 2009 1 次提交
  35. 29 5月, 2009 2 次提交
    • M
      [ARM] Add cmpxchg support for ARMv6+ systems (v5) · ecd322c9
      由 Mathieu Desnoyers 提交于 
      Add cmpxchg/cmpxchg64 support for ARMv6K and ARMv7 systems
(original patch from Catalin Marinas <catalin.marinas@arm.com>)

The cmpxchg and cmpxchg64 functions can be implemented using the
LDREX*/STREX* instructions. Since operand lengths other than 32bit are
required, the full implementations are only available if the ARMv6K
extensions are present (for the LDREXB, LDREXH and LDREXD instructions).

For ARMv6, only 32-bits cmpxchg is available.

Mathieu :

Make cmpxchg_local always available with best implementation for all type sizes (1, 2, 4 bytes).
Make cmpxchg64_local always available.

Use "Ir" constraint for "old" operand, like atomic.h atomic_cmpxchg does.

Change since v3 :
- Add "memory" clobbers (thanks to Nicolas Pitre)
- removed __asmeq(), only needed for old compilers, very unlikely on ARMv6+.

Note : ARMv7-M should eventually be ifdefed-out of cmpxchg64. But it's not
supported by the Linux kernel currently.

Put back arm < v6 cmpxchg support.
Signed-off-by: NMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Nicolas Pitre <nico@cam.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ecd322c9
    • R
      [ARM] barriers: improve xchg, bitops and atomic SMP barriers · bac4e960
      由 Russell King 提交于 
      Mathieu Desnoyers pointed out that the ARM barriers were lacking:

- cmpxchg, xchg and atomic add return need memory barriers on
  architectures which can reorder the relative order in which memory
  read/writes can be seen between CPUs, which seems to include recent
  ARM architectures. Those barriers are currently missing on ARM.

- test_and_xxx_bit were missing SMP barriers.

So put these barriers in.  Provide separate atomic_add/atomic_sub
operations which do not require barriers.
Reported-Reviewed-and-Acked-by: NMathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      bac4e960
  37. 25 3月, 2009 1 次提交
  39. 20 3月, 2009 1 次提交
    • R
      [ARM] pass reboot command line to arch_reset() · be093beb
      由 Russell King 提交于 
      OMAP wishes to pass state to the boot loader upon reboot in order to
instruct it whether to wait for USB-based reflashing or not.  There is
already a facility to do this via the reboot() syscall, except we ignore
the string passed to machine_restart().

This patch fixes things to pass this string to arch_reset().  This means
that we keep the reboot mode limited to telling the kernel _how_ to
perform the reboot which should be independent of what we request the
boot loader to do.
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      be093beb
  41. 29 11月, 2008 1 次提交
  43. 07 11月, 2008 1 次提交
  45. 01 9月, 2008 1 次提交
  47. 03 8月, 2008 1 次提交
  49. 23 5月, 2008 1 次提交
  51. 08 2月, 2008 1 次提交
  53. 10 1月, 2008 1 次提交
  55. 20 7月, 2007 1 次提交
  57. 09 5月, 2007 4 次提交
  59. 22 4月, 2007 1 次提交
  61. 02 4月, 2007 1 次提交
  63. 02 3月, 2007 1 次提交
  65. 08 2月, 2007 1 次提交