1. 10 8月, 2017 2 次提交
  2. 08 8月, 2017 1 次提交
    • C
      powerpc/32: Fix boot failure on non 6xx platforms · 64d0a506
      Christophe Leroy 提交于
      Commit d300627c ("powerpc/6xx: Handle DABR match before calling
      do_page_fault") breaks non 6xx platforms.
      
        Failed to execute /init (error -14)
        Starting init: /bin/sh exists but couldn't execute it (error -14)
        Kernel panic - not syncing: No working init found.  Try passing init= ...
        CPU: 0 PID: 1 Comm: init Not tainted 4.13.0-rc3-s3k-dev-00143-g7aa62e972a56 #56
        Call Trace:
          panic+0x108/0x250 (unreliable)
          rootfs_mount+0x0/0x58
          ret_from_kernel_thread+0x5c/0x64
        Rebooting in 180 seconds..
      
      This is because in handle_page_fault(), the call to do_page_fault() has been
      mistakenly enclosed inside an #ifdef CONFIG_6xx
      
      Fixes: d300627c ("powerpc/6xx: Handle DABR match before calling do_page_fault")
      Brown-paper-bag-to-be-worn-by: NMichael Ellerman <mpe@ellerman.id.au>
      Signed-off-by: NChristophe Leroy <christophe.leroy@c-s.fr>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      64d0a506
  3. 03 8月, 2017 3 次提交
  4. 02 8月, 2017 1 次提交
  5. 01 8月, 2017 2 次提交
    • V
      powerpc/kernel: Avoid preemption check in iommu_range_alloc() · 75f327c6
      Victor Aoqui 提交于
      Replace the __this_cpu_read() with raw_cpu_read() in
      iommu_range_alloc(). Otherwise we get a warning about using
      __this_cpu_read() in preemptible code:
      
        BUG: using __this_cpu_read() in preemptible
        caller is iommu_range_alloc+0xa8/0x3d0
      
      Preemption doesn't need to be disabled since according to the comment
      any CPU can safely use any IOMMU pool.
      Signed-off-by: NVictor Aoqui <victora@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      75f327c6
    • G
      powerpc/powernv: Save/Restore additional SPRs for stop4 cpuidle · e1c1cfed
      Gautham R. Shenoy 提交于
      The stop4 idle state on POWER9 is a deep idle state which loses
      hypervisor resources, but whose latency is low enough that it can be
      exposed via cpuidle.
      
      Until now, the deep idle states which lose hypervisor resources (eg:
      winkle) were only exposed via CPU-Hotplug.  Hence currently on wakeup
      from such states, barring a few SPRs which need to be restored to
      their older value, rest of the SPRS are reinitialized to their values
      corresponding to that at boot time.
      
      When stop4 is used in the context of cpuidle, we want these additional
      SPRs to be restored to their older value, to ensure that the context
      on the CPU coming back from idle is same as it was before going idle.
      
      In this patch, we define a SPR save area in PACA (since we have used
      up the volatile register space in the stack) and on POWER9, we restore
      SPRN_PID, SPRN_LDBAR, SPRN_FSCR, SPRN_HFSCR, SPRN_MMCRA, SPRN_MMCR1,
      SPRN_MMCR2 to the values they had before entering stop.
      Signed-off-by: NGautham R. Shenoy <ego@linux.vnet.ibm.com>
      Reviewed-by: NNicholas Piggin <npiggin@gmail.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      e1c1cfed
  6. 18 7月, 2017 2 次提交
  7. 13 7月, 2017 4 次提交
  8. 11 7月, 2017 1 次提交
    • N
      powerpc/powernv: Fix local TLB flush for boot and MCE on POWER9 · 41d0c2ec
      Nicholas Piggin 提交于
      There are two cases outside the normal address space management
      where a CPU's local TLB is to be flushed:
      
        1. Host boot; in case something has left stale entries in the
           TLB (e.g., kexec).
      
        2. Machine check; to clean corrupted TLB entries.
      
      CPU state restore from deep idle states also flushes the TLB.
      However this seems to be a side effect of reusing the boot code to set
      CPU state, rather than a requirement itself.
      
      The current flushing has a number of problems with ISA v3.0B:
      
      - The current radix mode of the MMU is not taken into account. tlbiel
        is undefined if the R field does not match the current radix mode.
      
      - ISA v3.0B hash must flush the partition and process table caches.
      
      - ISA v3.0B radix must flush partition and process scoped translations,
        partition and process table caches, and also the page walk cache.
      
      Add POWER9 cases to handle these, with radix vs hash determined by the
      host MMU mode.
      Signed-off-by: NNicholas Piggin <npiggin@gmail.com>
      Reviewed-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      41d0c2ec
  9. 10 7月, 2017 1 次提交
  10. 08 7月, 2017 1 次提交
  11. 03 7月, 2017 9 次提交
  12. 02 7月, 2017 1 次提交
  13. 28 6月, 2017 11 次提交
  14. 27 6月, 2017 1 次提交