1. 07 8月, 2014 1 次提交
  2. 04 8月, 2014 2 次提交
  3. 31 7月, 2014 1 次提交
  4. 30 7月, 2014 1 次提交
  5. 22 7月, 2014 5 次提交
  6. 16 7月, 2014 1 次提交
  7. 15 7月, 2014 2 次提交
  8. 14 7月, 2014 1 次提交
    • T
      ALSA: hda - Revert stream assignment order for Intel controllers · cd50065b
      Takashi Iwai 提交于
      We got a regression report for 3.15.x kernels, and this turned out to
      be triggered by the fix for stream assignment order.  On reporter's
      machine with Intel controller (8086:1e20) + VIA VT1802 codec, the
      first playback slot can't work with speaker outputs.
      
      But the original commit was actually a fix for AMD controllers where
      no proper GCAP value is returned, we shouldn't revert the whole
      commit.  Instead, in this patch, a new flag is introduced to determine
      the stream assignment order, and follow the old behavior for Intel
      controllers.
      
      Fixes: dcb32ecd ('ALSA: hda - Do not assign streams in reverse order')
      Reported-and-tested-by: NSteven Newbury <steve@snewbury.org.uk>
      Cc: <stable@vger.kernel.org> [v3.15+]
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      cd50065b
  9. 08 7月, 2014 3 次提交
  10. 07 7月, 2014 3 次提交
  11. 04 7月, 2014 1 次提交
  12. 01 7月, 2014 2 次提交
  13. 30 6月, 2014 1 次提交
  14. 27 6月, 2014 9 次提交
  15. 26 6月, 2014 1 次提交
    • M
      ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display controller · a07187c9
      Mengdong Lin 提交于
      For Intel Haswell/Broadwell display HD-A controller, the 24MHz HD-A link BCLK
      is converted from Core Display Clock (CDCLK): BCLK = CDCLK * M / N
      And there are two registers EM4 and EM5 to program M, N value respectively.
      The EM4/EM5 values will be lost and when the display power well is disabled.
      
      BIOS programs CDCLK selected by OEM and EM4/EM5, but BIOS has no idea about
      display power well on/off at runtime. So the M/N can be wrong if non-default
      CDCLK is used when the audio controller resumes, which results in an invalid
      BCLK and abnormal audio playback rate. So this patch saves and restores valid
      M/N values on controller suspend/resume.
      
      And 'struct hda_intel' is defined to contain standard HD-A 'struct azx' and
      Intel specific fields, as Takashi suggested.
      Signed-off-by: NMengdong Lin <mengdong.lin@intel.com>
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      a07187c9
  16. 25 6月, 2014 5 次提交
  17. 24 6月, 2014 1 次提交