1. 02 10月, 2007 1 次提交
    • D
      [SPARC64]: Fix missing load-twin usage in Niagara-1 memcpy. · 25e5566e
      David S. Miller 提交于
      For the case where the source is not aligned modulo 8
      we don't use load-twins to suck the data in and this
      kills performance since normal loads allocate in the
      L1 cache (unlike load-twin) and thus big memcpys swipe
      the entire L1 D-cache.
      
      We need to allocate a register window to implement this
      properly, but that actually simplifies a lot of things
      as a nice side-effect.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      25e5566e
  2. 20 3月, 2007 1 次提交
    • D
      [SPARC64]: store-init needs trailing membar. · 24d559ca
      David S. Miller 提交于
      The manual says that it is required and we actually have crash reports
      where loads see stale data due to not having membars here.
      
      In one case the networking does:
      
      	memset(skb, 0, offsetof(struct sk_buff, truesize));
      
      and then some code later checks skb->nohdr for zero, but it's still
      the value that was there before the memset().
      
      Note that arch/sparc64/lib/xor.S already got this right.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      24d559ca
  3. 20 3月, 2006 2 次提交