Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Changing eg 0xffffffff to DMA_BIT_MASK(32) etc allows easier
side by side comparision of identical code which can be consolidated.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This patch makes the various mach dirs that use the plat-orion time
code pass in timer and bridge addresses explicitly, instead of having
plat-orion get those values by including a mach dir include file --
the latter mechanism is problematic if you want to support multiple
ARM platforms in the same kernel image.
Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
CC: Saeed Bishara <saeed@marvell.com>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NChris Ball <cjb@laptop.org>

Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

The (void *) cast is not needed when setting dev.platform_data to the
address of the data. Remove the casts.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>