1. 03 9月, 2015 1 次提交
  2. 22 6月, 2015 1 次提交
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      MIPS: ath79: Improve the DDR controller interface · 24b0e3e8
      Alban Bedel 提交于
      The DDR controller need to be used by the IRQ controller to flush
      the write buffer of some devices before running the IRQ handler.
      It is also used by the PCI controller to setup the PCI memory windows.
      
      The current interface used to access the DDR controller doesn't
      provides any useful abstraction and simply rely on a shared global
      pointer.
      
      Replace this by a simple API to setup the PCI memory windows and use
      the write buffer flush independently of the SoC type. That remove the
      need for the shared global pointer, simplify the IRQ handler code.
      
      [ralf@linux-mips.org: Folded in Alban Bedel's follup fix.]
      Signed-off-by: NAlban Bedel <albeu@free.fr>
      Cc: linux-mips@linux-mips.org
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: Wolfram Sang <wsa@the-dreams.de>
      Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com>
      Cc: Gabor Juhos <juhosg@openwrt.org>
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9773/
      Patchwork: http://patchwork.linux-mips.org/patch/10543/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      24b0e3e8
  3. 01 4月, 2015 1 次提交
  4. 25 1月, 2014 1 次提交
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  6. 19 1月, 2011 2 次提交