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  1. 02 11月, 2011 15 次提交
  3. 15 9月, 2011 1 次提交
  5. 27 7月, 2011 1 次提交
  7. 26 7月, 2011 1 次提交
  9. 28 6月, 2011 1 次提交
  11. 25 5月, 2011 3 次提交
  13. 29 4月, 2011 1 次提交
  15. 15 4月, 2011 1 次提交
  17. 25 3月, 2011 1 次提交
    • T
      percpu: Always align percpu output section to PAGE_SIZE · 0415b00d
      由 Tejun Heo 提交于 
      Percpu allocator honors alignment request upto PAGE_SIZE and both the
percpu addresses in the percpu address space and the translated kernel
addresses should be aligned accordingly.  The calculation of the
former depends on the alignment of percpu output section in the kernel
image.

The linker script macros PERCPU_VADDR() and PERCPU() are used to
define this output section and the latter takes @align parameter.
Several architectures are using @align smaller than PAGE_SIZE breaking
percpu memory alignment.

This patch removes @align parameter from PERCPU(), renames it to
PERCPU_SECTION() and makes it always align to PAGE_SIZE.  While at it,
add PCPU_SETUP_BUG_ON() checks such that alignment problems are
reliably detected and remove percpu alignment comment recently added
in workqueue.c as the condition would trigger BUG way before reaching
there.

For um, this patch raises the alignment of percpu area.  As the area
is in .init, there shouldn't be any noticeable difference.

This problem was discovered by David Howells while debugging boot
failure on mn10300.
Signed-off-by: NTejun Heo <tj@kernel.org>
Acked-by: NMike Frysinger <vapier@gentoo.org>
Cc: uclinux-dist-devel@blackfin.uclinux.org
Cc: David Howells <dhowells@redhat.com>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: user-mode-linux-devel@lists.sourceforge.net
      0415b00d
  19. 23 3月, 2011 1 次提交
  21. 25 1月, 2011 1 次提交
    • T
      percpu: align percpu readmostly subsection to cacheline · 19df0c2f
      由 Tejun Heo 提交于 
      Currently percpu readmostly subsection may share cachelines with other
percpu subsections which may result in unnecessary cacheline bounce
and performance degradation.

This patch adds @cacheline parameter to PERCPU() and PERCPU_VADDR()
linker macros, makes each arch linker scripts specify its cacheline
size and use it to align percpu subsections.

This is based on Shaohua's x86 only patch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Shaohua Li <shaohua.li@intel.com>
      19df0c2f
  23. 12 11月, 2010 1 次提交
  25. 27 10月, 2010 3 次提交
  27. 21 8月, 2010 1 次提交
  29. 11 8月, 2010 1 次提交
  31. 03 8月, 2010 1 次提交
    • H
      um, x86: Cast to (u64 *) inside set_64bit() · bf676945
      由 H. Peter Anvin 提交于 
      After tightening up the types passed to set_64bit(), the cast to
(phys_t *) triggers a warning apparently because phys_t is defined as
"unsigned long" when building on 64 bits; however, u64 is defined as
"unsigned long long".  This is, however, a explicit cast inside a
size-specific call, so just make the cast explicitly (u64 *).
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
Cc: Jeff Dike <jdike@addtoit.com>
LKML-Reference: <tip-69309a05@git.kernel.org>
      bf676945
  33. 11 6月, 2010 1 次提交
  35. 14 5月, 2010 1 次提交
  37. 20 4月, 2010 1 次提交
  39. 13 3月, 2010 2 次提交
  41. 21 2月, 2010 1 次提交
    • R
      MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself · 4b3073e1
      由 Russell King 提交于 
      On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies.  We do this via make_coherent() by making the pages
uncacheable.

This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().

Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():

  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
  to construct a pointer to the pte again.  Passing a pte_t * is much
  more elegant.  Maybe we might even replace the pte argument with the
  pte_t?

Ben Herrenschmidt would also like the pte pointer for PowerPC:

  Passing the ptep in there is exactly what I want.  I want that
  -instead- of the PTE value, because I have issue on some ppc cases,
  for I$/D$ coherency, where set_pte_at() may decide to mask out the
  _PAGE_EXEC.

So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.

Includes a fix from Stephen Rothwell:

  sparc: fix fallout from update_mmu_cache API change
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      4b3073e1