- 04 10月, 2006 1 次提交
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由 Uwe Zeisberger 提交于
Many files include the filename at the beginning, serveral used a wrong one. Signed-off-by: NUwe Zeisberger <Uwe_Zeisberger@digi.com> Signed-off-by: NAdrian Bunk <bunk@stusta.de>
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- 22 9月, 2006 1 次提交
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由 Scott Wood 提交于
This patch fixes the assignment of pending registers to IRQ numbers for the IPIC; the code previously assigned all IRQs to the high pending word regardless of which word the interrupt belonged to. Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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- 30 8月, 2006 1 次提交
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由 Kim Phillips 提交于
This converts ipic code to Benh's IRQ mods. For the IPIC, IRQ sense values in the device tree equal those in include/linux/irq.h; that's 8 for low assertion (most internal IRQs on mpc83xx), and 2 for high-to-low change. spinlocks added to [un]mask, ack operations; default handler and type now set in host_map; and redundant condition check eliminated. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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- 30 6月, 2006 1 次提交
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由 Ingo Molnar 提交于
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: NIngo Molnar <mingo@elte.hu> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NAndrew Morton <akpm@osdl.org> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 09 1月, 2006 1 次提交
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由 Kumar Gala 提交于
Moved 83xx and QUICC Engine interrupt handling code into arch/powerpc as a precursor of getting 83xx sub-arch building in arch/powerpc. Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NPaul Mackerras <paulus@samba.org>
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- 26 6月, 2005 1 次提交
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由 Kumar Gala 提交于
The pending registers for IRQ1-IRQ7 were pointing to the interrupt pending register instead of the external one. Signed-off-by: NTony Li <Tony.Li@freescale.com> Signed-off-by: NKumar Gala <kumar.gala@freescale.com> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 24 5月, 2005 1 次提交
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由 Kumar Gala 提交于
There is an off-by-one error in the IPIC code that configures the external interrupts (Edge or Level Sensitive). Signed-off-by: NRandy Vinson <rvinson@mvista.com> Signed-off-by: NKumar Gala <kumar.gala@freescale.com> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 17 4月, 2005 1 次提交
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由 Linus Torvalds 提交于
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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