- 02 1月, 2014 2 次提交
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由 Chen-Yu Tsai 提交于
This patch adds the clock output pin options on the A20. The 2 pins can output a configurable clock to be used by external modules. This is used on the CubieTruck, to supply a 32768 Hz low power clock to the onboard Wifi+BT module. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Hans de Goede 提交于
Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 29 12月, 2013 4 次提交
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由 Emilio López 提交于
mbus is the memory bus clock, and it is present on both sun5i and sun7i machines. Its register layout is compatible with the mod0 one. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Emilio López 提交于
This commit adds all the mod0 clocks available on A20 to its device tree. This list was created by looking at AW's code release. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Emilio López 提交于
This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i device trees. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Emilio López 提交于
This commit adds the PLL4 definition to the sun4i, sun5i and sun7i device trees. PLL4 is compatible with PLL1. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 23 11月, 2013 2 次提交
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由 Emilio López 提交于
U-Boot uses the ethernet0 alias to locate the right node to fill in the MAC address of the first ethernet interface. This patch adds the alias on all the sunxi SoCs with EMAC. In this way, people using ethernet in U-Boot (eg, for tftp) can keep a consistent address on both U-Boot and Linux with no additional effort. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Carlo Caione 提交于
Add the RTC node to DTS for Allwinner A10 and Allwinner A20. Signed-off-by: NCarlo Caione <carlo.caione@gmail.com> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 19 9月, 2013 2 次提交
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由 Maxime Ripard 提交于
The A20 boards we currently have share the same pins for the i2c controllers they share. Add them to the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The Allwinner A20 shares the same I2C controller than the one that could be found on earlier SoCs from Allwinner. There is only a few more of these controllers. Add all of them in the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 17 9月, 2013 1 次提交
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由 Oliver Schinagl 提交于
This patch shall add support for the sunxi-sid driver to the device tree for A10, A10s, A13 and A20. Signed-off-by: NOliver Schinagl <oliver@schinagl.nl> Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 13 9月, 2013 2 次提交
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由 Maxime Ripard 提交于
The A20 has several muxing options for the EMAC. Yet, the currently supported boards only use one set of them. Add that pin set to the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Maxime Ripard 提交于
The Allwinner A20 SoC also have the EMAC found on the A10 and A10s. Enable the support for it in the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 26 8月, 2013 1 次提交
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由 Maxime Ripard 提交于
Now that the clock driver knows about the available clocks found on the A20, we can build up the clock tree from the device tree. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 22 8月, 2013 2 次提交
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由 Maxime Ripard 提交于
The UARTs on the A20 can be muxed to several pins. Add a few options to the DTSI so that we can start using them in the boards' DT. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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由 Maxime Ripard 提交于
The PIO controller is responsible for the GPIO/muxing/external interrupts handling. Now that we have support for the A20 pin set in the pinctrl driver, we can start using it in the DTSI. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 20 8月, 2013 1 次提交
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由 Maxime Ripard 提交于
The Allwinner A20 SoC is based on 2 Cortex A7, an ARM Mali GPU, and is built to be pin-compatible with the older Allwinner A10. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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- 17 8月, 2013 1 次提交
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由 Maxime Ripard 提交于
The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a PowerVR GPU. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
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