- 23 7月, 2009 4 次提交
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由 Nicolas Ferre 提交于
It seems that thread_count is not properly calculated in dmatest. In fact the thread count number that is returned from dmatest_add_threads() is not correctly added to the thread_count and thus not properly printed. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Acked-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Nicolas Ferre 提交于
The dmatest usually waits for the killing of its kthreads to stop running tests. This patch adds a parameter that sets a maximum number of test iterations. This feature is quite interesting for debugging when you set a lot of traces in your dmaengine controller driver. Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Joe Perches 提交于
Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Joe Perches 提交于
Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 02 7月, 2009 1 次提交
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由 Dan Williams 提交于
On HIGHMEM64G systems dma_addr_t is known to be larger than (void *) which precludes async_xor from performing dma address conversions by reusing the input parameter address list. However, other parts of the dmaengine infrastructure do not suffer this constraint, so the HIGHMEM64G restriction can be down-levelled. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 17 6月, 2009 3 次提交
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由 Ira Snyder 提交于
The 83xx controller does not support the external pause feature. The bit in the mode register that controls external pause on the 85xx controller happens to be part of the bandwidth control settings for the 83xx controller. This patch fixes the driver so that it only clears the external pause bit if the hardware is the 85xx controller. When driving the 83xx controller, the bit is left untouched. This follows the existing convention that mode registers settings are not touched unless necessary. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Ira Snyder 提交于
The 83xx controller has external start capability, but lacks external pause capability. Hook up the external start function pointer for the 83xx controller. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Ira W. Snyder 提交于
By default, the Freescale 83xx DMA controller uses the PCI Read Line command when reading data over the PCI bus. Setting the controller to use the PCI Read Multiple command instead allows the controller to read much larger bursts of data, which provides a drastic speed increase. The slowdown due to using PCI Read Line was only observed when a PCI-to-PCI bridge was between the devices trying to communicate. A simple test driver showed an increase from 4MB/sec to 116MB/sec when performing DMA over the PCI bus. Using DMA to transfer between blocks of local SDRAM showed no change in performance with this patch. The dmatest driver was also used to verify the correctness of the transfers, and showed no errors. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Acked-by: NTimur Tabi <timur@freescale.com> Acked-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 29 5月, 2009 1 次提交
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由 Len Brown 提交于
Testing the i7300_idle driver on i5000-series hardware required an edit to i7300_idle.h to "#define SUPPORT_I5000 1" and a re-build of both i7300_idle and ioat_dma. Replace that build-time scheme with a load-time module parameter: "7300_idle.forceload=1" to make it easier to test the driver on hardware that while not officially validated, works fine and is much more commonly available. By default (no modparam) the driver will continue to load only on the i7300. Note that ioat_dma runs a copy of i7300_idle's probe routine to know to reserve an IOAT channel for i7300_idle. This change makes ioat_dma do that always on the i5000, just like it does on the i7300. Signed-off-by: NLen Brown <len.brown@intel.com> Acked-by: NAndrew Henroid <andrew.d.henroid@intel.com>
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- 28 5月, 2009 1 次提交
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由 Kumar Gala 提交于
We we build with dma_addr_t as a 64-bit quantity we get: drivers/dma/fsldma.c: In function 'fsl_chan_xfer_ld_queue': drivers/dma/fsldma.c:625: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'fsl_dma_chan_do_interrupt': drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size drivers/dma/fsldma.c: In function 'of_fsl_dma_probe': drivers/dma/fsldma.c:927: warning: cast to pointer from integer of different Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 22 5月, 2009 5 次提交
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由 Ira Snyder 提交于
When preparing a memcpy operation, if the kernel fails to allocate memory for a link descriptor after the first link descriptor has already been allocated, then some memory will never be released. Fix the problem by walking the list of allocated descriptors backwards, and freeing the allocated descriptors back into the DMA pool. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Signed-off-by: NLi Yang <leoli@freescale.com>
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由 Ira Snyder 提交于
On the 83xx controller, snooping is necessary for the DMA controller to ensure cache coherence with the CPU when transferring to/from RAM. The last descriptor in a chain will always have the End-of-Chain interrupt bit set, so we can set the snoop bit while adding the End-of-Chain interrupt bit. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Signed-off-by: NLi Yang <leoli@freescale.com>
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由 Ira Snyder 提交于
When creating a DMA transaction with multiple descriptors, the async_tx cookie is set to 0 for each descriptor in the chain, excluding the last descriptor, whose cookie is set to -EBUSY. When fsl_dma_tx_submit() is run, it only assigns a cookie to the first descriptor. All of the remaining descriptors keep their original value, including the last descriptor, which is set to -EBUSY. After the DMA completes, the driver will update the last completed cookie to be -EBUSY, which is an error code instead of a valid cookie. This causes dma_async_is_complete() to always return DMA_IN_PROGRESS. This causes the fsldma driver to never cleanup the queue of link descriptors, and the driver will re-run the DMA transaction on the hardware each time it receives the End-of-Chain interrupt. This causes an infinite loop. With this patch, fsl_dma_tx_submit() is changed to assign a cookie to every descriptor in the chain. The rest of the code then works without problems. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Signed-off-by: NLi Yang <leoli@freescale.com>
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由 Ira Snyder 提交于
When using the DMA controller from multiple threads at the same time, it is possible to get lots of "DMA halt timeout!" errors printed to the kernel log. This occurs due to a race between fsl_dma_memcpy_issue_pending() and the interrupt handler, fsl_dma_chan_do_interrupt(). Both call the fsl_chan_xfer_ld_queue() function, which does not protect against concurrent accesses to dma_halt() and dma_start(). The existing spinlock is moved to cover the dma_halt() and dma_start() functions. Testing shows that the "DMA halt timeout!" errors disappear. Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu> Signed-off-by: NLi Yang <leoli@freescale.com>
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由 Roel Kluin 提交于
Fix the check of potential array overflow when using corrupted channel device tree nodes. Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NLi Yang <leoli@freescale.com>
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- 13 5月, 2009 2 次提交
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由 Guennadi Liakhovetski 提交于
This also fixes the case of a single queued buffer, for example, when taking a single frame snapshot with the mx3_camera driver. Reported-by: NAgustin Ferrin Pozuelo <gatoguan-os@yahoo.com> Tested-by: NAgustin Ferrin Pozuelo <gatoguan-os@yahoo.com> Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Maciej Sosnowski 提交于
as reported by Alexander Beregalov <a.beregalov@gmail.com> ioatdma 0000:00:08.0: DMA-API: device driver frees DMA memory with wrong function [device address=0x000000007f76f800] [size=2000 bytes] [map ped as single] [unmapped as page] The ioatdma driver was unmapping all regions (either allocated as page or single) using unmap_page. This patch lets dma driver recognize if unmap_single or unmap_page should be used. It introduces two new dma control flags: DMA_COMPL_SRC_UNMAP_SINGLE and DMA_COMPL_DEST_UNMAP_SINGLE. They should be set to indicate dma driver to do dma-unmapping as single (first one for the source, tha latter for the destination). If respective flag is not set, the driver assumes dma-unmapping as page. Signed-off-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Reported-by: NAlexander Beregalov <a.beregalov@gmail.com> Tested-by: NAlexander Beregalov <a.beregalov@gmail.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 06 5月, 2009 1 次提交
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由 Ben Nizette 提交于
disable_irq() should wait for all running handlers to complete before returning. As such, if it's used to disable an interrupt from that interrupt's handler it will deadlock. This replaces the dangerous instances with the _nosync() variant which doesn't have this problem. Note the 2 handlers in question are only used #ifdef DEBUG so I imagine these code paths don't get hit often. Signed-off-by: NBen Nizette <bn@niasdigital.com> Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 09 4月, 2009 1 次提交
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由 Dan Williams 提交于
The check for reaching max_channels is short circuited by 'continuing' after successfully adding a channel. [ Impact: make the 'max_channels' module parameter actually have an effect ] Cc: <stable@kernel.org> Reported-by: NDan Carpenter <error27@gmail.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 07 4月, 2009 2 次提交
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由 Yang Hongyang 提交于
Replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32) Signed-off-by: Yang Hongyang<yanghy@cn.fujitsu.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Yang Hongyang 提交于
Replace all DMA_64BIT_MASK macro with DMA_BIT_MASK(64) Signed-off-by: Yang Hongyang<yanghy@cn.fujitsu.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 03 4月, 2009 1 次提交
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由 Guennadi Liakhovetski 提交于
Add Start-of-Frame and End-of-Frame debugging to ipu_idmac.c, in the future it might also be needed for the actual video processing in mx3-camera, at which point, the ISRs will have to be transferred to mx3_camera.c, for which ipu_irq_map() and ipu_irq_unmap() functions will have to be exported. Also simplify a couple of pointer-dereferences. Signed-off-by: NGuennadi Liakhovetski <lg@denx.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 02 4月, 2009 1 次提交
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由 Hans-Christian Egtvedt 提交于
This patch adds a cyclic DMA interface to the DW DMA driver. This is very useful if you want to use the DMA controller in combination with a sound device which uses cyclic buffers. Using a DMA channel for cyclic DMA will disable the possibility to use it as a normal DMA engine until the user calls the cyclic free function on the DMA channel. Also a cyclic DMA list can not be prepared if the channel is already active. Signed-off-by: NHans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Acked-by: NHaavard Skinnemoen <haavard.skinnemoen@atmel.com> Acked-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 27 3月, 2009 1 次提交
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由 Atsushi Nemoto 提交于
Currently dma_request_channel() set DMA_PRIVATE capability but never clear it. So if a public channel was once grabbed by dma_request_channel(), the device stay PRIVATE forever. Add privatecnt member to dma_device to correctly revert it. [lg@denx.de: fix bad usage of 'chan' in dma_async_device_register] Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Acked-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 26 3月, 2009 8 次提交
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由 Dan Williams 提交于
Use the callback infrastructure to report driver/hardware hangs or missed interrupts. Since this makes the test threads much more aggressive (from: explicit 1ms sleep to: wait_for_completion) we set the nice value to 10 so as to not swamp legitimate tasks. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Extend dmatest to launch a thread per supported operation type and add an xor test. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Provide a config option for blocking the allocation of dma channels to the async_tx api. Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Centralize this common initialization (and one case where ipu_idmac is duplicating ->chan initialization). Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Guennadi Liakhovetski 提交于
Add DMA error handling to the ISR, move common code fragments to functions, fix scatter-gather element queuing in the ISR, survive channel freeing and re-allocation in a quick succession. Signed-off-by: NGuennadi Liakhovetski <lg@denx.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Guennadi Liakhovetski 提交于
The i.MX31 IPU DMA driver is a platform driver, but doesn't need hotplug, so we can use __init and __exit function attributes. Signed-off-by: NGuennadi Liakhovetski <lg@denx.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Guennadi Liakhovetski 提交于
Remove superfluous semicolons, update comments. Signed-off-by: NGuennadi Liakhovetski <lg@denx.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Atsushi points out: "If alloc_percpu or kzalloc failed, chan_id does not match with its position in device->channels list. And above "continue" looks buggy anyway. Keeping incomplete channels in device->channels list looks very dangerous..." Also, fix up leakage of idr_ref in the idr_pre_get() and channel init fail cases. Reported-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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- 25 3月, 2009 1 次提交
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由 Kay Sievers 提交于
Cc: Dan Williams <dan.j.williams@intel.com> Acked-by: NGreg Kroah-Hartman <gregkh@suse.de> Signed-off-by: NKay Sievers <kay.sievers@vrfy.org>
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- 13 3月, 2009 1 次提交
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由 Sascha Hauer 提交于
This patch adds clkdev support for i.MX31. This is done in a similar way done previously for i.MX27 Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 05 3月, 2009 6 次提交
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由 Dan Williams 提交于
dmatest_cleanup_chanel will free dtc, so grab ->chan before it goes away and use it to do the release. Reported-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Luotao Fu 提交于
fix a probably accidently dropped reference operator while calling spin_unlock_restore to an ipu lock. Signed-off-by: NLuotao Fu <l.fu@pengutronix.de> Cc: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Roel Kluin 提交于
iop_adma_zero_sum_self_test has the brackets in the wrong place for the setup failure deallocation path. This error was duplicated in mv_xor_xor_self_test. Signed-off-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
Prevent dev_err from firing even if we successfully detected 'dma-idle' before the full 1ms timeout has elapsed. Acked-by: NRoel Kluin <roel.kluin@gmail.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Dan Williams 提交于
If we miss interrupts in the self test then fail registration of this channel as it is unsuitable for use as a public channel. Signed-off-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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由 Maciej Sosnowski 提交于
Together with new fixes update driver version and extend copyright dates ranges. Signed-off-by: NMaciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: NShannon Nelson <shannon.nelson@intel.com> Acked-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: NDan Williams <dan.j.williams@intel.com>
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