Topic branch set up to facilitate merging the rest of the series which
removes the driver from arch code.

From local branch irqchip/gic, this is topic branch that was set up to
facilitate merging other changes depending on the new GICv3 driver.

Define SoCs that need irq fixups before enabling the AIC irqchip.

At the moment we're only fixing irq generated by the RTC block, but other
fixups will be added later on.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Link: https://lkml.kernel.org/r/1405016741-2407-4-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Provide an implementation to fix RTC irqs before enabling the irqchip.

This was previously done in arch/arm/mach-at91/sysirq_mask.c but as we're
trying to use standard implementation (IRQCHIP_DECLARE and automatic call
of irqchip_init within arch/arm/kernel/irq.c) we need to do those fixups
in the irqchip driver.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Link: https://lkml.kernel.org/r/1405016741-2407-3-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Add irq fixup infrastructure to handle IP blocks connected to shared irqs
that are left in an unknown state when booting the kernel.

In this case the IP block which has not masked its interrupt and has no
driver loaded (either because it is not compiled or because it is not
loaded yet) might generate spurious interrupts when another IP block
request the shared irq.

A good example of this case is the RTC block on which register configs are
kept even after a shutdown (if a proper VDDcore is supplied), and thus
might generate spurious interrupts when the platform is switched on.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Link: https://lkml.kernel.org/r/1405016741-2407-2-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Add AIC (Advanced Interrupt Controller) and AIC5 (AIC5 is an evolution of
the AIC block) drivers.
Put common code in irq-atmel-aic-common.c/.h so that both driver can access
shared functions (this will ease maintenance).

These drivers are only compatible with dt enabled board and replace the
old implementation found in arch/arm/mach-at91/irq.c.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Link: https://lkml.kernel.org/r/1405012462-766-4-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Move atmel aic driver doc to the interrupt-controller directory as the new
driver now lays in drivers/irqchip/atmel-aic.c.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Link: https://lkml.kernel.org/r/1405012462-766-3-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Export the generic irq map function in order to provide irq_domain ops with
generic mapping and specific of xlate function (needed by the new atmel
AIC driver).
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/1405012462-766-2-git-send-email-boris.brezillon@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Generic Interrupt Controller (version 3) offers services that are
similar to GICv2, with a number of additional features:
- Affinity routing based on the CPU MPIDR (ARE)
- System register for the CPU interfaces (SRE)
- Support for more that 8 CPUs
- Locality-specific Peripheral Interrupts (LPIs)
- Interrupt Translation Services (ITS)

This patch adds preliminary support for GICv3 with ARE and SRE,
non-secure mode only. It relies on higher exception levels to grant ARE
and SRE access.

Support for LPI and ITS will be added at a later time.

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: NZi Shen Lim <zlim@broadcom.com>
Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: NTirumalesh Chalamarla <tchalamarla@cavium.com>
Reviewed-by: NYun Wu <wuyun.wu@huawei.com>
Reviewed-by: NZhen Lei <thunder.leizhen@huawei.com>
Tested-by: Tirumalesh Chalamarla<tchalamarla@cavium.com>
Tested-by: NRadha Mohan Chintakuntla <rchintakuntla@cavium.com>
Acked-by: NRadha Mohan Chintakuntla <rchintakuntla@cavium.com>
Acked-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: NMark Rutland <mark.rutland@arm.com>
Link: https://lkml.kernel.org/r/1404140510-5382-3-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

A few GICv2 low-level function are actually very useful to GICv3,
and it makes some sense to share them across the two drivers.
They end-up in their own file, with an additional parameter used
to ensure an optional synchronization (unused on GICv2).

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Acked-by: NChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1404140510-5382-2-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In addition to consolidating the or1k-pic with other interrupt
controllers, this makes OpenRISC less tied to its on-cpu
interrupt controller.

All or1k-pic specific parts are moved out of irq.c and into
drivers/irqchip/irq-or1k-pic.c

In that transition, the functionality have been divided into
three chip variants.
One that handles level triggered interrupts, one that handles edge
triggered interrupts and one that handles the interrupt
controller that is present in the or1200 OpenRISC cpu
implementation.
Signed-off-by: NStefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Link: https://lkml.kernel.org/r/1401136302-27654-1-git-send-email-stefan.kristiansson@saunalahti.fiAcked-by: NJonas Bonn <jonas@southpole.se>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

On certain platforms such as DRA7, SPIs 0, 1, 2, 3, 5, 6, 10, 131,
132, 133 are direct wired to hardware blocks bypassing crossbar.
This quirky implementation is *NOT* supposed to be the expectation
of crossbar hardware usage. However, these are already marked in our
description of the hardware with SKIP and RESERVED where appropriate.

Unfortunately, we need to be able to refer to these hardwired IRQs.
So, to request these, crossbar driver can use the existing information
from it's table that these SKIP/RESERVED maps are direct wired sources
and generic allocation/programming of crossbar should be avoided.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-17-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The current crossbar description does not include the description
required for the consumer of the crossbar, a.k.a devices whoes events
pass through the crossbar into the GIC interrupt controller.

So, provide documentation for the same.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-16-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This is a basic check to ensure that crossbar register needs to be
written. This ensures that we have a common check which is used in
both map and unmap logic.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-15-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Currently we attempt to map any crossbar value to an IRQ, however,
this is not correct from hardware perspective. There is a max crossbar
event number upto which hardware supports. So describe the same in
device tree using 'ti,max-crossbar-sources' property and use it to
validate requests.

[ jac - remove MAX_SOURCES from binding doc, use integer because we
shouldn't put implementation details in the binding docs ]
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-14-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Adding kerneldoc for unmap callback function.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-13-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

If crossbar_of_init returns with a error, then set the cb pointer
to null.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-12-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Using err1,2,3,4 etc makes it hard to ensure a new exit path in the
middle will not result in spurious changes, so rename the error paths
as per the function it does.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-11-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

crossbar_of_init always returns -ENOMEM in case of errors.
There can be other causes of failure like invalid data from
DT. So return a appropriate error value for that case.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-10-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Adding missing properties for kerneldoc (@write) and cleanup
of harmless warnings while we are here.

kerneldoc warnings:
Warning(drivers/irqchip/irq-crossbar.c:27): missing initial short description on line:
 * struct crossbar_device: crossbar device description
Info(drivers/irqchip/irq-crossbar.c:27): Scanning doc for struct
Warning(drivers/irqchip/irq-crossbar.c:39): No description found for parameter 'write'
2 warnings
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-9-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

There is absolutely no need for crossbar driver to expose functions and
variables into global namespace. So make them all static

Also fix a couple of checkpatch warnings.

Fixes sparse warnings:
drivers/irqchip/irq-crossbar.c:129:29: warning: symbol 'routable_irq_domain_ops' was not declared. Should it be static?
drivers/irqchip/irq-crossbar.c:261:12: warning: symbol 'irqcrossbar_init' was not declared. Should it be static?

Checkpatch warnings:
WARNING: Prefer kcalloc over kzalloc with multiply
+	cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL);

WARNING: Prefer kcalloc over kzalloc with multiply
+	cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-8-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

IS_ERR_VALUE makes sense only *if* there could be valid values in
negative error range. But in the cases that we do use it, there is no
such case. Just remove the same.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-7-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Reverse the search algorithm to ensure that address mapping and IRQ
allocation logics are proper. This makes the below bugs visible sooner.

class 1. address space errors -> example:
reg = <a size_b>
ti,max-irqs =  is a wrong parameter

class 2: irq-reserved list - which decides which entries in the
address space is not actually wired in

class 3: wrong list of routable-irqs.

In general allocating from max to min tends to have benefits in
ensuring the different issues that may be present in dts is easily
caught at definition time, rather than at a later point in time.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-6-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Since crossbar is s/w configurable, the initial settings of the
crossbar cannot be assumed to be sane. This implies that:
a) On initialization all un-reserved crossbars must be initialized to
   a known 'safe' value.
b) When unmapping the interrupt, the safe value must be written to
   ensure that the crossbar mapping matches with interrupt controller
   usage.

So provide a safe value in the dt data to map if
'0' is not safe for the platform and use it during init and unmap

While at this, fix the below checkpatch warning.
Fixes checkpatch warning:
WARNING: Unnecessary space before function pointer arguments
 #37: FILE: drivers/irqchip/irq-crossbar.c:37:
 +	void (*write) (int, int);
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-5-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

When, in the system due to varied reasons, interrupts might be unusable
due to hardware behavior, but register maps do exist, then those interrupts
should be skipped while mapping irq to crossbars.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-4-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

If irq_of_parse_and_map is executed twice, the same crossbar is mapped to two
different GIC interrupts. This is completely undesirable. Instead, check
if the requested crossbar event is pre-allocated and provide that GIC
mapping back to caller if already allocated.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-3-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Today '0' is actually reserved, but may not be the same in the future.

So, use a flag to mark the GIC interrupts that are reserved.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-2-git-send-email-r.sricharan@ti.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The extra register data structure is pointless. Move the offsets of
the status and the mask register into the shirq block structure.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.923306179@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Only spear300 has an actual mask register for the RAS interrupts. Add
an irq chip pointer to the shirq struct and initialize spear300 with
the actual implementation and the others with dummy_irq_chip. The
disabled RAS3 block has no irq chip assigned, so we can check for this
and remove the disabled member.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.831341023@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

"ack" is actually a mask in the parent irq. The demultiplexer and the
handlers run with interrupts disabled. No point in masking and
unmasking the parent.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.754300980@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

I don't know if there are less efficient ways to code that. Get rid of
the loop mess and use efficient code.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.662897061@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

None of the chips has a ACK register. The code brainlessly fiddles
with the enable register, so it might even reenable a disabled
interrupt at least on spear300.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.570396433@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Calculate the status mask at compile time, not at runtime.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.496614337@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

No point in doing a full irq lookup, when the desc pointer is
available.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.404243909@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Order the ras blocks in the order of interrupts not alphabetically.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.310591579@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The struct members of the shirq block struct are named to confuse the
hell out of the casual reader. Clean it up.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.219411832@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The struct member is pointless and a nismomer as well.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.129694036@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

No point in having them in a separate header file. Make the init
functions static.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212713.038658058@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Link: https://lkml.kernel.org/r/20140619212712.948802939@linutronix.deAcked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>