This adds the clocksource driver for Cirrus Logic CLPS711X series SoCs.
Designed primarily for migration CLPS711X subarch for multiplatform & DT,
for this as the "OF" and "non-OF" calls implemented.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

In the clocksource driver, we didn't explicitly enable the clock. it makes the
clk reference counter wrong. We didn't encounter any hang issue because the
tick's clock input has been open and is shared by some other hardware
components, but if we don't enable those components in kernel, in the stage of
disabling unused clk in kernel boot, Linux tick hangs.

This patch fixes it. it does an explicit prepare and enable to the clock input,
and increases the usage counter of the clk.
Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

In 'em_sti.c', it will call devm_ioremap_resource() which need
HAS_IOMEM. So need let EM_TIMER_STI depend on HAS_IOMEM, too.

The related error (with allmodconfig under score):

  LD      init/built-in.o
em_sti.c:(.text.em_sti_probe+0x84): undefined reference to `devm_ioremap_resource'
make: *** [vmlinux] Error 1
Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.

The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.

Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Purpose Timer block can be run with two clocks. A 13 MHz system
clock and the RTC clock running at 32 KHz. This implementation uses the system
clock with no clock source divider.

The interrupts are shared between the different timers and have to be read back
from a register. We just enable one interrupt for the clock event. The clock
event timer is used by all cores.
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

It should be "MTU2" instead of "TMU2"
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NWolfram Sang <wsa@sang-engineering.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This patch registers the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for
the exynos platform and avoid using unnecessary calibrated
jiffies. This change has been tested on exynos5420 based board and
udelay is very close to expected.

Without this patch udelay() on exynos5400 / exynos5800 is wildly
inaccurate due to big.LITTLE not adjusting loops_per_jiffy correctly.
Also without this patch udelay() on exynos5250 can be innacruate
during transitions between frequencies < 800 MHz (you'll go 200 MHz ->
800 MHz -> 300 MHz and will run at 800 MHz for a time with the wrong
loops_per_jiffy).

[dianders: reworked and created version 3]
Signed-off-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In (93bfb769 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock.  We properly marked
exynos4_read_sched_clock() as notrace.  However, we then went and
called another function that _wasn't_ notrace.  That means if you do:

  cd /sys/kernel/debug/tracing/
  echo function_graph > current_tracer

You'll get a crash.

Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function.  It's important to keep other users of MCT
traceable because the MCT is actually quite slow to access and we want
exynos4_frc_read() to show up in ftrace profiles if it's the
bottleneck.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Document DT bindings and parse them in the MTU2 driver.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NWolfram Sang <wsa@sang-engineering.com>

Document DT bindings and parse them in the TMU driver.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Document DT bindings and parse them in the CMT driver.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

The global spinlock is used to protect the shared start/stop register.
Now that all MTU2 channels are handled by a single device instance, use
a per-device spinlock.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NWolfram Sang <wsa@sang-engineering.com>

Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NWolfram Sang <wsa@sang-engineering.com>

The global spinlock is used to protect the shared start/stop register.
Now that all TMU channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

The global spinlock is used to protect the shared start/stop register.
Now that all CMT channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Move the clocksource Kconfig entries into their own menu, so that they
don't pollute the main device driver menu.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/20140616114845.343e9960@endymion.delvareSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Unfortunately on some exynos systems, resetting the mct counter also
resets the architected timer counter.  This can cause problems if the
architected timer driver has already been initialized because the kernel
will think that the counter has wrapped around, causing a big jump in
printk timestamps and delaying any scheduled clock events until the
counter reaches the value it had before it was reset.

The kernel code makes no assumptions about the initial value of the mct
counter so there is no reason from a software perspective to clear the
counter before starting it.  This also fixes the problems described in
the previous paragraph.

Cc: Olof Johansson <olof@lixom.net>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NChirantan Ekbote <chirantan@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The newly merged versatile sched clock support uses a deprecated
interface.  Of course that patch got routed through the ARM tree instead
of going through the relevant maintainer tree.

Use the proper interface so we can get rid of the cruft.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.

This patch tries to rectify that:

* the mach-vexpress code cannot link without the syscfg driver,
  which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
  has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
  available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
  be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
  use modern timekeeping but rely on gettimeoffset.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The Freescale FlexTimer Module time reference is a 16-bit counter
that can be used as an unsigned or signed increase counter.

CNTIN defines the starting value of the count and MOD defines the
final value of the count. The value of CNTIN is loaded into the FTM
counter, and the counter increments until the value of MOD is reached,
at which point the counter is reloaded with the value of CNTIN. That's
also when an overflow interrupt will be generated.

Here using the 'evt' prefix or postfix as clock event device and
the 'src' as clock source device.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.

[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.

[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.

[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

We do not need to trace read_sched_clock function,
so add notrace attribute for this function.
Signed-off-by: NYang Wei <Wei.Yang@windriver.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

For some clocksource devices, for example, the registers are 32-bit, while
the lower 16-bit is used for timer counting(And reading the upper 16-bit
will return 0).

For example, when the counter value is 0x00001111, and then the
~readl_relaxed(to_mmio_clksrc(c)->reg) will return the value of 0xFFFFEEEE,
but it should be 0x0000EEEE.

So just using the c->mask to mask the unused bits.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The types' definations are:
   o  cycle_t       -> u64
   o  readl_relaxed -> u32
   o  readw_relaxed -> u16

So let clocksource_mmio_readX_Ys return a cast to cycle_t, though
this maybe look reduntant sometimes, it make sense and they will be
more readable and less confusion...

This patch clarifies the functions type and fix it.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

tc_mode() can be called from interrupt context and thus must not call
clk_*prepare*() functions.
Signed-off-by: NDavid Jander <david@protonic.nl>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

irqchip will reject the affinity set to CPUs which is not online
yet. but in the CPU1 wakeup stage, OS only sets CPU1 to be online
after local timer is set, so that causes the irq_set_affinity not
work. this patch moves to irq_force_affinity() for the low level
boot stage.
Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

We now have several OF match tables using linker sections that are
nearly the same definition. The only variation is the callback function
prototype. Create a common define for creating linker section OF match
table entries which each table declaration can use.
Acked-by: NGrant Likely <grant.likely@linaro.org>
Signed-off-by: NRob Herring <robh@kernel.org>

For supporting ARM big-endian is necessary to use
proper IO endianess accessors.

Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38a)
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

In the legacy platform data case each TMU platform device handles a
single channel with a single IRQ for the platform device. Retrieve the
IRQ using the logical channel number instead of the hardware channel
number.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This patch adds a trival sched clock source using free
running, 24MHz clocked counter present in the ARM Ltd.
reference platforms (Versatile, RealView, Versatile
Express) System Registers block.

This code replaces the call in the VE machine code.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

Nobody want to know the connection between io clk and timer clk,
so exposing this information to timer module is not reasonable.
this patch moves to define the timers' clk in dt.
Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>

Fix the "line over 80 characters". users of the codes - key customers
really care about that.

WARNING: line over 80 characters
64: FILE: timer-prima2.c:64:
+       WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));

WARNING: line over 80 characters
80: FILE: timer-prima2.c:80:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
82: FILE: timer-prima2.c:82:
+       cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

WARNING: line over 80 characters
92: FILE: timer-prima2.c:92:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
96: FILE: timer-prima2.c:96:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
111: FILE: timer-prima2.c:111:
+               writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

WARNING: line over 80 characters
114: FILE: timer-prima2.c:114:
+               writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

WARNING: line over 80 characters
126: FILE: timer-prima2.c:126:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
129: FILE: timer-prima2.c:129:
+               sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

WARNING: line over 80 characters
137: FILE: timer-prima2.c:137:
+               writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

WARNING: line over 80 characters
139: FILE: timer-prima2.c:139:
+       writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);

WARNING: line over 80 characters
140: FILE: timer-prima2.c:140:
+       writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);

WARNING: line over 80 characters
216: FILE: timer-prima2.c:216:
+CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init);

total: 0 errors, 13 warnings, 216 lines checked

timer-prima2.c has style problems, please review.

If any of these errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.
Signed-off-by: NBin Shi <Bin.Shi@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>

Use the clocksource mct-frc for sched_clock
Signed-off-by: NVincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: NTomasz Figa <t.figa@samsung.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

CC      drivers/clocksource/zevio-timer.o
drivers/clocksource/zevio-timer.c:215:1: warning: comparison of distinct pointer types lacks a cast [enabled by default]
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

ARM arch timers are tightly coupled with the CPU logic and lose context
on platform implementing HW power management when cores are powered
down at run-time. Marking the arch timers as C3STOP regardless of power
management capabilities causes issues on platforms with no power management,
since in that case the arch timers cannot possibly enter states where the
timer loses context at runtime and therefore can always be used as a high
resolution clockevent device.

In order to fix the C3STOP issue in a way compliant with how real HW
works, this patch adds a boolean property to the arch timer bindings
to define if the arch timer is managed by an always-on power domain.

This power domain is present on all ARM platforms to date, and manages
HW that must not be turned off, whatever the state of other HW
components (eg power controller). On platforms with no power management
capabilities, it is the only power domain present, which encompasses
and manages power supply for all HW components in the system.

If the timer is powered by the always-on power domain, the always-on
property must be present in the bindings which means that the timer cannot
be shutdown at runtime, so it is not a C3STOP clockevent device.
If the timer binding does not contain the always-on property, the timer is
assumed to be power-gateable, hence it must be defined as a C3STOP
clockevent device.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>