1. 16 10月, 2008 1 次提交
  2. 19 8月, 2008 13 次提交
  3. 18 8月, 2008 1 次提交
  4. 17 8月, 2008 6 次提交
  5. 16 8月, 2008 2 次提交
  6. 15 8月, 2008 4 次提交
  7. 14 8月, 2008 1 次提交
    • M
      x86: resurrect proper handling of maxcpus= kernel option (v2) · 23b49c19
      Max Krasnyansky 提交于
      For some reason we had two parsers registered for maxcpus=. One in init/main.c
      and another in arch/x86/smpboot.c. So I nuked the one in arch/x86.
      
      Also 64-bit kernels used to handle maxcpus= as documented in
      Documentation/cpu-hotplug.txt. CPUs with 'id > maxcpus' are initialized
      but not booted. 32-bit version for some reason ignored them even though
      all the infrastructure for booting them later is there.
      
      In the current mainline both 64 and 32 bit versions are broken.
      This patch restores the correct behaviour. I've tested x86_64 version on
      4- and 8- way Core2 and 2-way Opteron based machines. Various config
      combinations SMP, !SMP, CPU_HOTPLUG, !CPU_HOTPLUG.
      Booted with maxcpus=1 and maxcpus=4, etc. Everything is working as expected.
      
      So far we've received two reports from different people confirming that 32-bit
      version also works fine, both on dual core laptops and 16way server machines.
      
      [v2: This version fixes visws breakage pointed out by Ingo.]
      Signed-off-by: NMax Krasnyansky <maxk@qualcomm.com>
      Cc: lizf@cn.fujitsu.com
      Cc: jeff.chua.linux@gmail.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      23b49c19
  8. 26 7月, 2008 3 次提交
  9. 24 7月, 2008 2 次提交
  10. 21 7月, 2008 1 次提交
  11. 20 7月, 2008 1 次提交
    • S
      x86: APIC: Remove apic_write_around(); use alternatives, merge fix · f586bf7d
      Suresh Siddha 提交于
      On Fri, Jul 18, 2008 at 02:03:48PM -0700, Ingo Molnar wrote:
      >
      > * Yinghai Lu <yhlu.kernel@gmail.com> wrote:
      >
      > > > git merge tip/x86/x2apic
      > > CONFLICT (content): Merge conflict in arch/x86/kernel/Makefile
      > > CONFLICT (content): Merge conflict in arch/x86/kernel/paravirt.c
      > > CONFLICT (content): Merge conflict in arch/x86/kernel/smpboot.c
      > > CONFLICT (content): Merge conflict in arch/x86/kernel/vmi_32.c
      > > CONFLICT (content): Merge conflict in arch/x86/xen/enlighten.c
      > > CONFLICT (content): Merge conflict in include/asm-x86/apic.h
      > > CONFLICT (content): Merge conflict in include/asm-x86/paravirt.h
      >
      > that's due to the changes in tip/x86/apic and in tip/x86/uv.
      >
      > ok, i've just merged x86/apic into x86/x2apic and x86/uv as well, and
      > pushed out the result.
      >
      > Note: it's a first raw merge and completely untested. It will now merge
      > cleanly into tip/master. There are probably a few details missing.
      
      Ingo, thanks for doing this. While I was testing my merge changes, you posted
      yours... anyhow we need this piece, which is missing from your merge.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: Yinghai Lu <yhlu.kernel@gmail.com>
      Cc: "Maciej W. Rozycki" <macro@linux-mips.org>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Zachary Amsden <zach@vmware.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      f586bf7d
  12. 18 7月, 2008 2 次提交
  13. 12 7月, 2008 3 次提交
    • Y
      x86: make read_apic_id return final apicid · 4c9961d5
      Yinghai Lu 提交于
      also remove GET_APIC_ID when read_apic_id is used.
      
      need to apply after
      	[PATCH] x86: mach_apicdef.h need to include before smp.h
      Signed-off-by: NYinghai Lu <yhlu.kernel@gmail.com>
      Cc: Suresh Siddha <suresh.b.siddha@intel.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      4c9961d5
    • S
      x64, x2apic/intr-remap: add x2apic support, including enabling interrupt-remapping · 6e1cb38a
      Suresh Siddha 提交于
      x2apic support.  Interrupt-remapping must be enabled before enabling x2apic,
      this is needed to ensure that IO interrupts continue to work properly after the
      cpu mode is changed to x2apic(which uses 32bit extended physical/cluster
      apic id).
      
      On systems where apicid's are > 255, BIOS can handover the control to OS in
      x2apic mode. Or if the OS handover was in legacy xapic mode, check
      if it is capable of x2apic mode. And if we succeed in enabling
      Interrupt-remapping, then we can enable x2apic mode in the CPU.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      6e1cb38a
    • S
      x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping · 89027d35
      Suresh Siddha 提交于
      IO-APIC support in the presence of interrupt-remapping infrastructure.
      
      IO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)
      index and the IRTE will contain information about the vector, cpu destination,
      trigger mode etc, which traditionally was present in the IO-APIC RTE.
      
      Introduce a new irq_chip for cleaner irq migration (in the process
      context as opposed to the current irq migration in the context of an interrupt.
      interrupt-remapping infrastructure will help us achieve this cleanly).
      
      For edge triggered, irq migration is a simple atomic update(of vector
      and cpu destination) of IRTE and flush the hardware cache.
      
      For level triggered, we need to modify the io-apic RTE aswell with the update
      vector information, along with modifying IRTE with vector and cpu destination.
      So irq migration for level triggered is little  bit more complex compared to
      edge triggered migration. But the good news is, we use the same algorithm
      for level triggered migration as we have today, only difference being,
      we now initiate the irq migration from process context instead of the
      interrupt context.
      
      In future, when we do a directed EOI (combined with cpu EOI broadcast
      suppression) to the IO-APIC, level triggered irq migration will also be
      as simple as edge triggered migration and we can do the irq migration
      with a simple atomic update to IO-APIC RTE.
      
      TBD: some tests/changes needed in the presence of fixup_irqs() for
      level triggered irq migration.
      Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com>
      Cc: akpm@linux-foundation.org
      Cc: arjan@linux.intel.com
      Cc: andi@firstfloor.org
      Cc: ebiederm@xmission.com
      Cc: jbarnes@virtuousgeek.org
      Cc: steiner@sgi.com
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      89027d35