Need to use the RREG32_SMC() accessor since the register
is an smc indirect index.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

If the new mc ucode is available.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

As per internal recommendations.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Setting higher mclks seems to cause stability issues
on some R7 260X boards.  Disable it for now for stability
until we find a proper fix.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=75992Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Some of the vce clocks are automatic, others need to
be manually enabled.  For ease, just disable cg when
vce is active.

v2: rebased
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

VCE dpm dynamically adjusts the uvd clocks on
demand.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It's needed by by both the asic specific functions and the
extended table parser.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Noticed by Rashika Kheria and cherry-picked from
her larger patch set.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: Rashika Kheria <rashika.kheria@gmail.com>

We need more control over the ordering of dpm init with
respect to the rest of the asic.  Specifically, the SMC
has to be initialized before the rlc and cg/pg.  The pm
code currently initializes late in the driver, but we need
it to happen much earlier so move pm handling into the asic
specific callbacks.

This makes dpm more reliable and makes clockgating work
properly on CIK parts and should help on SI parts as well.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Right now it's called right after enable, but after
reworking the dpm init order, it will get called later
to accomodate loading the smc early, but enabling
thermal interrupts and block powergating later after
the ring tests are complete.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Make sure interrupts are enabled
before we enable thermal interrupts.
Also, don't powergate uvd until after
the ring tests.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

I'm not entirely sure this is required and it won't work
with the dpm restructing anyway.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This updates the CI dpm (dynamic power management)
support for hawaii.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Filter out mclk and sclk levels higher than listed in the clk
voltage dependency tables.  Supporting these clocks will require
additional driver tweaking that isn't supported yet.

See bug:
https://bugs.freedesktop.org/show_bug.cgi?id=68235Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Calling force_performance_level() from set_power_state()
doesn't work on some asics because the current power
state pointer has not been properly updated at that point.
Move the calls to force_performance_level() out of the
asic specific set_power_state() functions and into
the main power state sequence.

Fixes dpm resume on SI.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Acked-by: NAlex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: NDave Airlie <airlied@gmail.com>

Check to make sure the dc limits are valid before using them.
Some systems may not have a dc limits table.  In that case just
use the ac limits.  This fixes hangs on systems when the power
state is changed when on battery (dc) due to invalid performance
state parameters.

Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=68708Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Newer versions of gcc seem to wander off into the
weeds when dealing with variable sizes arrays in
structs.  Rather than indexing the arrays, use
pointer arithmetic.

See bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=66932
https://bugs.freedesktop.org/show_bug.cgi?id=66972
https://bugs.freedesktop.org/show_bug.cgi?id=66945Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Track the current uvd gated state on CI to avoid unnecessary
state changes when uvd is active.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

UVD dpm dynamically adjusts the uvd clocks on
demand.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Disable the UVD block when not in use to save power.
The block is not actually powergated on CI, but we
switch between UVD DPM (where the uvd clocks are
adjusted on demand) and clocks off.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Allows you to force the selected performance level via sysfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows you to look at the current DPM state via debugfs.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>