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  1. 22 5月, 2010 1 次提交
  3. 01 5月, 2010 2 次提交
  5. 13 4月, 2010 1 次提交
  7. 27 2月, 2010 2 次提交
  9. 11 2月, 2010 1 次提交
  11. 28 1月, 2010 1 次提交
    • D
      MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs · 010c108d
      由 David VomLehn 提交于 
      The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      010c108d
  13. 17 12月, 2009 2 次提交
  15. 18 9月, 2009 1 次提交
  17. 17 6月, 2009 2 次提交
  19. 30 3月, 2009 1 次提交
  21. 24 3月, 2009 1 次提交
  23. 31 1月, 2009 2 次提交
  25. 11 1月, 2009 1 次提交
  27. 30 10月, 2008 2 次提交
  29. 11 10月, 2008 1 次提交
  31. 04 10月, 2008 1 次提交
  33. 21 9月, 2008 1 次提交
  35. 06 9月, 2008 2 次提交
  37. 31 7月, 2008 1 次提交
    • J
      [MIPS] kgdb: add arch support for the kernel's kgdb core · 88547001
      由 Jason Wessel 提交于 
      The new kgdb architecture specific handler registers and unregisters
dynamically for exceptions depending on when you configure a kgdb I/O
driver.

Aside from initializing the exceptions earlier in the boot process,
kgdb should have no impact on a device when it is compiled in so long
as an I/O module is not configured for use.

There have been quite a number of contributors during the existence of
this patch (see arch/mips/kernel/kgdb.c).  Most recently Jason
re-wrote the mips kgdb logic to use the die notification handlers.
Signed-off-by: NJason Wessel <jason.wessel@windriver.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      88547001
  39. 16 7月, 2008 2 次提交
  41. 06 6月, 2008 1 次提交
  43. 29 4月, 2008 3 次提交
  45. 12 3月, 2008 2 次提交
  47. 15 12月, 2007 1 次提交
  49. 16 11月, 2007 1 次提交
    • R
      [MIPS] Fix shadow register support. · f6771dbb
      由 Ralf Baechle 提交于 
      Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f6771dbb
  51. 20 10月, 2007 1 次提交
  53. 19 10月, 2007 1 次提交
  55. 18 10月, 2007 1 次提交
    • M
      [MIPS] SYNC emulation for MIPS I processors · 60b0d655
      由 Maciej W. Rozycki 提交于 
      Userland, including the C library and the dynamic linker, is keen to use
the SYNC instruction, even for "generic" MIPS I binaries these days.
Which makes it less than useful on MIPS I processors.

This change adds the emulation, but as our do_ri() infrastructure was not
really prepared to take yet another instruction, I have rewritten it and
its callees slightly as follows.

Now there is only a single place a possible signal is thrown from.  The
place is at the end of do_ri().  The instruction word is fetched in
do_ri() and passed down to handlers.  The handlers are called in sequence
and return a result that lets the caller decide upon further processing.
If the result is positive, then the handler has picked the instruction,
but a signal should be thrown and the result is the signal number.  If the
result is zero, then the handler has successfully simulated the
instruction.  If the result is negative, then the handler did not handle
the instruction; to make it more obvious the calls do not follow the usual
0/-Exxx result convention they now return -1 instead of -EFAULT.

The calculation of the return EPC is now at the beginning.  The reason is
it is easier to handle it there as emulation callees may modify a register
and an instruction may be located in delay slot of a branch whose result
depends on the register.  It has to be undone if a signal is to be raised,
but it is not a problem as this is the slow-path case, and both actions
are done in single places now rather than the former being scattered
through emulation handlers.

The part of do_cpu() being covered follows the changes to do_ri().
Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

---
      60b0d655
  57. 17 10月, 2007 1 次提交
    • R
      [MIPS] IP22: Fix warning. · eae23f2c
      由 Ralf Baechle 提交于 
        CC      arch/mips/sgi-ip22/ip22-berr.o
arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt':
arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      eae23f2c