Otherwise IOMEM calculations can fail.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Some bootloader may initialize debounce register and this will make
dbclk not consist with the debounce register after linux kernel boot
up.
Signed-off-by: Njanboe <janboe.ye@gmail.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The function flush_iotlb_page is not loading the CAM register with
the correct entry to be flushed, so it is flushing other entry
Signed-off-by: NFernando Guzman Lugo <x0095840@ti.com>
Signed-off-by: NHiroshi DOYU <Hiroshi.DOYU@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch enables MStandby smart-idle mode, autoidle smartidle mode,
and the autoidle bit for DMA4_OCP_SYSCONFIG.
Signed-off-by: NKalle Jokiniemi <ext-kalle.jokiniemi@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@ti.deeprootsystems.com>

SRAM size fix for HS/EMU devices
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The omap_type() function is added and returns the DEVICETYPE field of
the CONTROL_STATUS register.  The result can be used for conditional
code based on whether device is GP (general purpose), EMU or
HS (high security). Also move the type defines so omap1 code
compile does not require ifdefs for sections using these defines.

This code is needed for the following fix to set the SRAM
size correctly for HS omaps.  Also at least PM and watchdog
code will need this function.
Signed-off-by: NKevin Hilman <khilman@ti.deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control.
Signed-off-by: NTero Kristo <tero.kristo@nokia.com>

Program the SDRC_MR_0 register as well during SDRC clock changes.
This register allows selection of the memory CAS latency.  Some SDRAM
chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency
at lower clock rates.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2
divider, add a short delay before returning to SDRAM to allow the SDRC
time to stabilize.  Without this delay, the system is prone to random
panics upon re-entering SDRAM.

This time delay varies based on MPU frequency.  At 500MHz MPU frequency at
room temperature, 64 loops seems to work okay; so add another 32 loops for
environmental and process variation.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This patch adds SMP platform specific parts for local(mpu) timer support
for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the
MPU domain. These timers are not in wakeup domain.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

This patch adds SMP platform files support for OMAP4430SDP. TI's OMAP4430
SOC is based on ARM Cortex-A9 SMP architecture. It's a dual core SOC
with GIC used for interrupt handling and SCU for cache coherency.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

Kconfig entries default to n, so there's no need for this to be
explicitly specified.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch updates the Makefile and Kconfig entries for OMAP4. The OMAP4430 SDP
board file supports only minimal set of drivers.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch update the common clock.c file for OMAP4. The clk_get() and
clk_put() functions are moved to  common place in arch/arm/common/clkdev.c
Since on current OMAP4 platform clk management is still not supported, the
platform file is stubbed with those functions.

Once the framework is ready, this WILL be replaced with a full
clkdev implementation.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch adds the support for OMAP4. The platform and machine specific
headers and sources updated for OMAP4430 SDP platform.

OMAP4430 is Texas Instrument's SOC based on ARM Cortex-A9 SMP architecture.
It's a dual core SOC with GIC used for interrupt handling and SCU for cache
coherency.
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Based on an earlier patches by Stanley.Miao <stanley.miao@windriver.com>
and Nishant Kamat <nskamat@ti.com>.

Note that at the ads7846 support still needs support for vaux_control
for the touchscreen to work.
Signed-off-by: NTony Lindgren <tony@atomide.com>

These are not being used right now, and the processor specific
defines should be used instead by any code accessing these registers.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Make 770 LCD work by adding clk_add_alias().
Also remove the old unused functions.

Note that the clk_add_alias() could probably be moved
to arch/arm/clkdev.c later on.

Cc: linux-fbdev-devel@lists.sourceforge.net
Signed-off-by: NAndrew de Quincey <adq_dvb@lidskialf.net>
Signed-off-by: NImre Deak <imre.deak@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com

Convert the board-rx51 smc91x code to be generic and make
the boards to use it. This allows future recalculation of the
timings when the source clock gets scaled.

Also correct the rx51 interrupt to be IORESOURCE_IRQ_HIGHLEVEL.

Thanks to Paul Walmsley <paul@pwsan.com> for better GPMC timing
calculations.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add generic onenand support when connected to GPMC and make the
boards to use it.

The patch has been modified to make it more generic to support all
the boards with GPMC. The patch also remove unused prototype for
omap2_onenand_rephase(void).

Note that board-apollon.c is currently using the MTD_ONENAND_GENERIC
and setting the GPMC timings in the bootloader. Setting the GPMC
timings in the bootloader will not allow supporting frequency
scaling for the onenand source clock.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Original OMAP DMA chaining design had chain_id as one of the callback
parameters. Patch 538528de changed it
to use logical channel instead.

Correct the naming for callback to also use logical channel number
instead of the chain_id.

More details are on this email thread:

http://marc.info/?l=linux-omap&m=122961071931459&w=2Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Implement transparent copy and constant fill features for OMAP2/3.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Otherwise, bootloaders may leave MUSB in a state which prevents
retention.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.

Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention.  The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup.  The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.

While the activity timer is active, the smart-idle mode of the UART is
also disabled.  This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.

Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.

In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.

Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.

Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)

Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Add common omap2/3 function to check wether there is irq pending.
Switch to use it in omap2 pm code instead of its own.
Signed-off-by: NJouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch is to sync the core linux-omap PM code with mainline.  This
code has evolved and been used for a while the linux-omap tree, but
the attempt here is to finally get this into mainline.

Following this will be a series of patches from the 'PM branch' of the
linux-omap tree to add full PM hardware support from the linux-omap
tree.

Much of this PM core code was written by Jouni Hogander with
significant contributions from Paul Walmsley as well as many others
from Nokia, Texas Instruments and linux-omap community.
Signed-off-by: NJouni Hogander <jouni.hogander@nokia.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch removes unnecessary omap2_globals and pass the global structures
directly as function argument.

The proposed cleanup was suggested by Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch removes fixes omap_sram_error() function and replace the
error paths with BUG_ON.

The proposed fix was suggested by Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This patch fixes the compiler warning "assignment from incompatible
pointer type"  in dmtimer.c and removes the tye casts. These warnings
were suppressed by type catsing.

The proposed fix was suggested by Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Processor specific macros should be used instead.
Signed-off-by: NTony Lindgren <tony@atomide.com>

It's currently unused, and processor specific defines should
be used instead.
Signed-off-by: NTony Lindgren <tony@atomide.com>

Move define of OMAP2_VA_IC_BASE to be local to entry-macro.S
Signed-off-by: NTony Lindgren <tony@atomide.com>

Remove OMAP_PRM_REGADDR and use processor specific defines instead.

Also fold in a patch from Kevin Hilman to add _OFFSET #defines
for the PRCM registers to be used with the prm_[read|write]_* macros.
These are used extensively in the forthcoming OMAP PM support.

Also remove now unused OMAP2_PRM_BASE.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Use processor specific defines instead.

As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK
calling sched_clock before we have things initialized:

http://patchwork.kernel.org/patch/15810/Signed-off-by: NTony Lindgren <tony@atomide.com>

This email address is going to expire soon so update it.
Signed-off-by: NJarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

If XSYNCERR or RSYNCERR interrupts are enabled, they are never
cleared causing the IRQ handler to be continuously called.
This patch clears the IRQs in question in the event they are
enabled and taken.
Signed-off-by: NEero Nurkkala <ext-eero.nurkkala@nokia.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This increases VMALLOC_END to 0x18000000, making room for 256MB
RAM with the default 128MB vmalloc region.

Note that after this patch there's no longer a hole between vmalloc
space and the beginning of IO space on omap2 as the first virtual
mapping starts at 0xd8000000.

Also fold in a related change from Paul Walmsley <paul@pwsan.com>
to change the OMAP2_SRAM addresses accordingly.
Signed-off-by: NMans Rullgard <mans@mansr.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Acked-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>