- 28 3月, 2017 1 次提交
-
-
由 Baruch Siach 提交于
Downstream kernel uses pins 32, 33 as UART0 (PL011) Rx/Tx to communicate with the Bluetooth chip. So ALT3 of these pins is most likely not CTS/RTS. Change the node name to reflect that. This matches section 6.2 "Alternative Function Assignments" in the BCM2835 ARM Peripherals document. With this change in place, adding &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>; status = "okay"; }; to bcm2837-rpi-3-b.dts does the right thing on my Raspberry Pi 3. Pins 30, 31 are CTS/RTS of UART0 in alternate function 3. Rename uart0_gpio30 as well. While at it, fix a little typo in a nearby comment. Fixes: 21ff8439 ("ARM: dts: bcm283x: Define standard pinctrl groups in the gpio node.") Acked-by: NStefan Wahren <stefan.wahren@i2se.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NEric Anholt <eric@anholt.net>
-
- 18 3月, 2017 1 次提交
-
-
由 Gerd Hoffmann 提交于
Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Acked-by: NEric Anholt <eric@anholt.net> Acked-by: NStefan Wahren <stefan.wahren@i2se.com>
-
- 17 3月, 2017 1 次提交
-
-
由 Boris Brezillon 提交于
Add the dmas and dma-names properties to support HDMI audio. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 07 3月, 2017 1 次提交
-
-
由 Eric Anholt 提交于
The modules stay disabled by default, and if you want to enable DSI you'll need an overlay that connects a panel to it. Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 19 1月, 2017 1 次提交
-
-
由 Boris Brezillon 提交于
Add the VEC (Video EnCoder) node definition in bcm283x.dtsi. Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 12 11月, 2016 1 次提交
-
-
由 Martin Sperl 提交于
Add the node for the thermal sensor of the bcm2835-soc to the device tree. Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Reviewed-by: NEric Anholt <eric@anholt.net> Acked-by: NStefan Wahren <stefan.wahren@i2se.com> Changelog: V1 -> V5: generic settings is shared in bcm283x.dtsi, but disabled moved the compatible string to the SOC specific dtsi for arm and arm64 V5 -> V6: fix remove 0x prefix from thermal@0x7e212000 Note: there is no arm/boot/dts/bcm2837.dtsi as of now, so the 32-bit rpi3 dt is not modified. Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 01 11月, 2016 1 次提交
-
-
由 Stefan Wahren 提交于
The address of the mailbox node in the bcm283x.dtsi also has a typo. So fix it accordingly. Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Fixes: 05b682b7 ("ARM: bcm2835: dt: Add the mailbox to the device tree") Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 18 10月, 2016 1 次提交
-
-
由 Eric Anholt 提交于
The BCM2835-ARM-Peripherals.pdf documentation specifies what the function selects do for the pins, and there are a bunch of obvious groupings to be made. With these created, we'll be able to replace bcm2835-rpi.dtsi's main "set all of these pins to alt0" with references to specific groups we want enabled. Also add pinctrl groups for emmc and sdhost. Based on patches by Eric Anholt, with fixups by Gerd Hoffmann. Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net> Acked-by: NStefan Wahren <stefan.wahren@i2se.com>
-
- 09 9月, 2016 1 次提交
-
-
由 Ian Campbell 提交于
This file is included from DTS files under arch/arm64 too (via broadcom/bcm2837-rpi-3-b.dts and broadcom/bcm2837.dtsi). There is a desire not to have skeleton.dtsi for ARM64. See commit 3ebee5a2 ("arm64: dts: kill skeleton.dtsi") for rationale for its removal. As well as the addition of #*-cells also requires adding the device_type to the rpi memory node explicitly. Note that this change results in the removal of an empty /aliases node from bcm2835-rpi-a.dtb and bcm2835-rpi-a-plus.dtb. I have no hardware to check if this is a problem or not. It also results in some reordering of the nodes in the DTBs (the /aliases and /memory nodes come later). This isn't supposed to matter but, again, I've no hardware to check if it is true in this particular case. Signed-off-by: NIan Campbell <ijc@hellion.org.uk> Acked-by: NMark Rutland <mark.rutland@arm.com> Tested-by: NStefan Wahren <stefan.wahren@i2se.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Frank Rowand <frowand.list@gmail.com> Cc: Eric Anholt <eric@anholt.net> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rpi-kernel@lists.infradead.org Cc: arm@kernel.org Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
- 25 8月, 2016 1 次提交
-
-
由 Stefan Wahren 提交于
According to the DWC2 binding an appropriate clock is required. This clock isn't handled by bcm2835 clock driver, so add a fixed clock to the bcm283x DT. Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 01 6月, 2016 1 次提交
-
-
由 Lubomir Rintel 提交于
The hub and the ethernet in its port 1 are hardwired on the board. Compared to the adapters that can be plugged into the USB ports, this one has no serial EEPROM to store its MAC. Nevertheless, the Raspberry Pi has the MAC address for this adapter in its ROM, accessible from its firmware. U-Boot can read out the address and set the local-mac-address property of the node with "ethernet" alias. Let's add the node so that U-Boot can do its business. Model B rev2 and Model B+ entries were verified by me, the hierarchy and pid/vid pair for the Version 2 was provided by Peter Chen. Original Model B is a blind shot, though very likely correct. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 20 4月, 2016 1 次提交
-
-
由 Eric Anholt 提交于
VC4 is the GPU (display and 3D) present on the 283x. Signed-off-by: NEric Anholt <eric@anholt.net> Acked-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 19 4月, 2016 1 次提交
-
-
由 Martin Sperl 提交于
Add interrupt-names properties to dt and apply the correct mapping between irq and dma channels. Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Acked-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NEric Anholt <eric@anholt.net> Signed-off-by: NVinod Koul <vinod.koul@intel.com>
-
- 18 2月, 2016 1 次提交
-
-
由 Martin Sperl 提交于
Add bcm2835-aux-uart support to the device tree. Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 03 2月, 2016 4 次提交
-
-
由 Alexander Aring 提交于
This connects the USB driver to the USB power domain, so that USB can actually be turned on at boot if the bootloader didn't do it for us. Signed-off-by: NAlexander Aring <alex.aring@gmail.com> Signed-off-by: NEric Anholt <eric@anholt.net> Reviewed-by: NKevin Hilman <khilman@linaro.org>
-
由 Martin Sperl 提交于
This patch fixes the naming of the device tree node: uart@7e201000 to conform to the standard of: serial@7e201000 Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> [anholt: Rebased on 2835.dtsi -> 283x.dtsi change] Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Remi Pommarel 提交于
Signed-off-by: NRemi Pommarel <repk@triplefau.lt> [anholt: Rebased on 2835.dtsi -> 283x.dtsi change] Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Martin Sperl 提交于
This enables the use of the auxiliary spi1 and spi2 devices on the bcm2835 SOC. Note that this requires the use of the new clk-bcm2835-aux to work. Signed-off-by: NMartin Sperl <kernel@martin.sperl.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> [anholt: Rebased on 2835.dtsi -> 283x.dtsi change] Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 01 1月, 2016 2 次提交
-
-
由 Eric Anholt 提交于
These will be used for enabling UART1, SPI1, and SPI2. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
由 Eric Anholt 提交于
The set of peripherals remained constant across bcm2835 (Raspberry Pi 1) and bcm2836 (Raspberry Pi 2), but the CPU was swapped out. Split the files so that we can include just peripheral setup in 2836. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
- 23 10月, 2015 2 次提交
-
-
由 Eric Anholt 提交于
We need to use it for getting video modes over HDMI. Signed-off-by: NEric Anholt <eric@anholt.net> Acked-by: NStephen Warren <swarren@wwwdotorg.org>
-
由 Eric Anholt 提交于
This will give us the ability to set the pixel and HDMI state machine clocks for the VC4 KMS driver, change the CPU frequency, and potentially gate clocks in the future (once we also write a power domain driver). It also gives the uart an explicit clock reference, so that we don't need to change the physical addresses of the old fixed clk_bcm2835.c clocks for Raspberry Pi 2 port. Two clocks get their frequencies updated as a result of this. One is uart's apb_pclk, which was previously accidentally grabbing the fixed uart0_pclk due to the apb_pclk not having clk_register_clkdev() called. The uart doesn't seem to do anything with apb_pclk other than make sure it's on, so that appears safe (also, as far as I can see, the apb clock is actually the same as the VPU clock). The other is EMMC, which according to the docs was supposed to be in the 50-100Mhz range, but it turns out the firmware needed to change to running it at the 250Mhz core clock speed to avoid a bug in clock domain crossing. Additionally, anything using BCM2835_CLOCK_VPU will now have a correct clock rate if the user configures the boot-time core clock speed using config.txt. Signed-off-by: NEric Anholt <eric@anholt.net> Acked-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 15 10月, 2015 1 次提交
-
-
由 Stefan Wahren 提交于
This patch adds a label for uart0 to allow changing of uart0 pins. Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 14 5月, 2015 4 次提交
-
-
由 Eric Anholt 提交于
There exists a tiny MMU, configurable only by the VC (running the closed firmware), which maps from the ARM's physical addresses to bus addresses. These bus addresses determine the caching behavior in the VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top 2 bits. The bits in the bus address mean: From the VideoCore processor: 0x0... L1 and L2 cache allocating and coherent 0x4... L1 non-allocating, but coherent. L2 allocating and coherent 0x8... L1 non-allocating, but coherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent From the GPU peripherals (note: all peripherals bypass the L1 cache. The ARM will see this view once through the VC MMU): 0x0... Do not use 0x4... L1 non-allocating, and incoherent. L2 allocating and coherent. 0x8... L1 non-allocating, and incoherent. L2 non-allocating, but coherent 0xc... SDRAM alias. Cache is bypassed. Not L1 or L2 allocating or coherent The 2835 firmware always configures the MMU to turn ARM physical addresses with 0x0 top bits to 0x4, meaning present in L2 but incoherent with L1. However, any bus addresses we were generating in the kernel to be passed to a device had 0x0 bits. That would be a reserved (possibly totally incoherent) value if sent to a GPU peripheral like USB, or L1 allocating if sent to the VC (like a firmware property request). By setting dma-ranges, all of the devices below it get a dev->dma_pfn_offset, so that dma_alloc_coherent() and friends return addresses with 0x4 bits and avoid cache incoherency. This matches the behavior in the downstream 2708 kernel (see BUS_OFFSET in arch/arm/mach-bcm2708/include/mach/memory.h). Signed-off-by: NEric Anholt <eric@anholt.net> Tested-by: NNoralf Trønnes <noralf@tronnes.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
-
由 Eric Anholt 提交于
Signed-off-by: NEric Anholt <eric@anholt.net> Acked-by: NLee Jones <lee.jones@linaro.org> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
-
由 Baruch Siach 提交于
Device tree node names should contain the node's reg property address value. The i2c0 node was apparently forgotten in commit 25b2f1bd (ARM: bcm2835: node name unit address cleanup). Acked-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NLee Jones <lee.jones@linaro.org>
-
由 Stefan Wahren 提交于
This patch converts all bcm2835 dts and dtsi files to use the pinctrl header file. Reviewed-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
-
- 26 9月, 2014 1 次提交
-
-
由 Mark Brown 提交于
Signed-off-by: NFlorian Meier <florian.meier@koalo.de> [Tweaked slightly to disable by default -- broonie] Signed-off-by: NMark Brown <broonie@linaro.org> [swarren, removed duplicate i2s node] Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
-
- 25 2月, 2014 1 次提交
-
-
由 Stephen Warren 提交于
DT nodes should be named according to the type of object that they represent rather than the identity. DT nodes that contain a reg property should include a unit address in their name. Fix these issues. Add clock-output-names properties to the nodes so that the clocks get named something meaningful. This works around the fact that the fixed clock driver names clocks after the short node name, i.e. not including the unit address. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 21 2月, 2014 1 次提交
-
-
由 Stephen Warren 提交于
DT nodes that contain a reg property should include a unit address in their name. Add the missing unit addresses. The unit address in a node name must match the value in the reg property. Fix the cases where they don't match. Don't fix the /clocks/* node names yet; that causes problems the clock driver to attempt to register multiple clocks with the same name, which fails. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 12 2月, 2014 4 次提交
-
-
由 Stephen Warren 提交于
Re-order all the DT nodes so that they're ordered by their reg address. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
由 Florian Meier 提交于
This adds the definitions for the BCM2835 I2S driver to the device tree. Some GPIO settings are needed for the correct pin functions. Signed-off-by: NFlorian Meier <florian.meier@koalo.de> [swarren: fixed DT node sort order, simplified DT label name, removed RPI .dts file changs, since use of I2S is a user-added option.] Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
由 Florian Meier 提交于
This adds the definitions for the BCM2835 dmaengine driver to the device tree. The dma-channel-mask is currently fixed. Later it should be set via the firmware. Signed-off-by: NFlorian Meier <florian.meier@koalo.de> [swarren, fixed DT node sort order] Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
由 Vince Weaver 提交于
The following patch enables performance counter support on Raspberry-Pi. We have this working on the 2708 based rasp-pi kernels by manually putting the device registration in the platform files. This change does things properly in a device tree. The boot messages look proper, but my rasp-pi hangs somewhere in USB enabling when running a stock 3.13-rc6 kernel so I have been unable to fully test this change. I also understand that the rasp-pi 1176 pmu support is missing the overflow interrupt. I'm not sure if that's true of all 2835 implementations. If not, then this patch will need to be changed a bit. Signed-off-by: NVince Weaver <vincent.weaver@maine.edu> [swarren, fixed DT node sort order] Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 03 1月, 2014 1 次提交
-
-
由 Stephen Warren 提交于
The BCM2835 SoC contains a DWC2 USB controller. Add this to the DT. Set up the pin controller to fully enable the USB controller on the Raspberry Pi. The GPIO setup works because the default output value for GPIO 6 (LAN_RUN/n_reset) just happens to be 1, which enables the USB/LAN chip. Note that you'll need a U-Boot which enables power to the USB controller; search for U-Boot patch "ARM: rpi_b: power on SDHCI and USB HW modules". Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
-
- 26 11月, 2013 1 次提交
-
-
由 Stephen Warren 提交于
The I2C controller node needs #address-cells and #size-cells properties, but these are currently missing. Add them. This allows child nodes to be parsed correctly. Cc: stable@vger.kernel.org Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
-
- 03 6月, 2013 1 次提交
-
-
由 Jongsung Kim 提交于
Stephen Warren reported the recent commit 78506f22 (add support for extended FIFO-size of PL011-r1p5) breaks the serial port on the BCM2835 ARM SoC. A UART compatible with the ARM PL011-r1p5 should have 32-deep FIFOs. The BCM2835 UART just looks like an ARM PL011-r1p5, but has 16-deep FIFOs just like PL011-r1p4 or earlier revisions. As a workaround for this compatibility issue, this patch overrides the HW UART periphid register values with the actually compatible UART periphid 0x00241011 (r1p3 or r1p4). Reported-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NJongsung Kim <neidhard.kim@lge.com> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
-
- 03 4月, 2013 1 次提交
-
-
由 Lubomir Rintel 提交于
This adds a device tree binding for random number generator present on Broadcom BCM2835 SoC, used in Raspberry Pi and Roku 2 devices. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Tested-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 12 3月, 2013 1 次提交
-
-
由 Stephen Warren 提交于
The BCM2835 has a single instance of the "SPI0"-type SPI master controller. Instantiate it in the SoC .dtsi file, Don't enable it in the Raspberry Pi board .dts file, since we have no idea what is actually connected, and hence no idea what to set the bus clock rate to. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
-
- 05 3月, 2013 1 次提交
-
-
由 Stephen Warren 提交于
BCM2835-ARM-Peripherals.pdf states that the I2C module's input clock is nominally 150MHz, and that value is currently reflected in bcm2835.dtsi. However, practical measurements show that the rate is actually 250MHz, and this agrees with various downstream kernels. Switch the I2C clock's frequency to 250MHz so that the generated bus clock rate is accurate. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
-