提交 · e9f9530bb697f53dd620df290102359a3325bb23 · openeuler / raspberrypi-kernel

22 9月, 2011 1 次提交

ath9k_hw: Fix Rx DMA stuck for AR9003 chips · e9f9530b

由 Rajkumar Manoharan 提交于 9月 20, 2011

During the endurance testing, rx frames are not getting DMAd from
MAC whereas pcu rx frame counters are getting updated properly.
As per systems team input updated the initval to fix rx dma stuck
issue.

Cc: stable@kernel.org
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

e9f9530b

08 7月, 2011 3 次提交

ath9k_hw: Remove read-only registers from AR9003 intervals · 1fa1238e

由 Rajkumar Manoharan 提交于 7月 08, 2011

This patch removes read only registers that cause invalid
address access and also updates index for measurement filter
calibration window size.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

1fa1238e

ath9k_hw: Disable power detector calibration for AR9003 · 43d9325b

由 Rajkumar Manoharan 提交于 7月 08, 2011

The power detector calibration is disabled because this block
doesn't exist in AR9003 based chips and also parallel
calibration is enabled otherwise the calibration will never stop.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

43d9325b

ath9k_hw: Update AR9003 interval to improve 5G Tx EVM · 6fea2b15

由 Rajkumar Manoharan 提交于 7月 08, 2011

The number of temperature reading samples to average
during a Tx packet is decreased to 1 from 2 to improve
5G Tx EVM with chain 0-only mode.
Signed-off-by: NRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

6fea2b15

20 5月, 2011 1 次提交

ath9k: Drag the driver to the year 2011 · 5b68138e

由 Sujith Manoharan 提交于 5月 17, 2011

The Times They Are a-Changin'.
Signed-off-by: NSujith Manoharan <Sujith.Manoharan@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

5b68138e

13 4月, 2011 2 次提交
- R
  ath9k_hw: update AR9003 low_ob_db_tx_gain to improve spur performance · 901c1113
  由 Rajkumar Manoharan 提交于 4月 11, 2011
```
Signed-off-by: NRajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
```
  901c1113
- R
  ath9k_hw: update Ar9003 intervals to fix carrier leak · 5fb32faf
  由 Rajkumar Manoharan 提交于 4月 11, 2011
```
Signed-off-by: NRajkumar Manoharan <rmanoharan@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
```
  5fb32faf
18 1月, 2011 1 次提交

ath9k_hw: ASPM interoperability fix for AR9380/AR9382 · 58c52969

由 Luis R. Rodriguez 提交于 1月 13, 2011

There is an interoperability with AR9382/AR9380 in L1 state with a
few root complexes which can cause a hang. This is fixed by
setting some work around bits on the PCIE PHY. We fix by using
a new ini array to modify these bits when the radio is idle.

Cc: stable@kernel.org
Cc: Jack Lee <jack.lee@atheros.com>
Cc: Carl Huang <carl.huang@atheros.com>
Cc: David Quan <david.quan@atheros.com>
Cc: Nael Atallah <nael.atallah@atheros.com>
Cc: Sarvesh Shrivastava <sarvesh.shrivastava@atheros.com>
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

58c52969

14 12月, 2010 2 次提交

F
ath9k_hw: update AR9003 initvals to improve carrier leak calibration/correction · 7a7793ef
由 Felix Fietkau 提交于 12月 13, 2010
```
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
```
7a7793ef

ath9k_hw: update AR9003 initvals for improved radar detection · e172e0f8

由 Felix Fietkau 提交于 12月 13, 2010

Reduces the likelihood of false pulse detects in the hardware
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

e172e0f8

26 10月, 2010 1 次提交

ath9k_hw: Fix TX carrier leakage for IEEE compliance on AR9003 2.2 · 0dfa6dbb

由 Luis R. Rodriguez 提交于 10月 18, 2010

This updates the initvals for the AR9003 2.2 chipsets. The initvals
are the initial register values we use for our registers upon hardware
reset. This synchs up the initvals to match what our latest recommendation
from our systems engineering team.

The description of changes in this update:

        Improves ability to support very strong Rx conditions.
        Enhances DFS support for AP-mode.
        Improves performance of Tx carrier leak calibration.
        Adds support for Japan channel 14 Tx filtering requirements.
        Improves Tx power accuracy.

Impact:

        Update required to address degraded throughput at very short range.
        Update required for AP-mode DFS certification.
        Update required to comply to IEEE Tx carrier leak specification.
        May not meet expected +/- 2 dB Tx power accuracy without update.

The most important fix here would be the TX carrier leakage required
to comply with IEEE 802.11 specifications. The group of changes have
been tested all together in one release.

References:

	Osprey 2.2 header file ver #33

Checksums:

$ ./initvals -f ar9003-2p2
0x000000004a488fc7        ar9300_2p2_radio_postamble
0x0000000046cb1300        ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e912711f        ar9300Modes_fast_clock_2p2
0x0000000037ac0ee8        ar9300_2p2_radio_core
0x00000000047a7700        ar9300Common_rx_gain_table_merlin_2p2
0x0000000003f783bb        ar9300_2p2_mac_postamble
0x00000000301fc841        ar9300_2p2_soc_postamble
0x000000005ec8075f        ar9200_merlin_2p2_radio_core
0x0000000083372ffa        ar9300_2p2_baseband_postamble
0x00000000c4f59974        ar9300_2p2_baseband_core
0x00000000e20d2e72        ar9300Modes_high_power_tx_gain_table_2p2
0x000000007fd55c70        ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000029495000        ar9300Common_rx_gain_table_2p2
0x0000000042cb1300        ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000c4739cd6        ar9300_2p2_mac_core
0x000000003521a300        ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a15ccf1b        ar9300_2p2_soc_preamble
0x0000000029734396        ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d834396        ar9300PciePhy_clkreq_enable_L1_2p2
0x0000000029834396        ar9300PciePhy_clkreq_disable_L1_2p2

$ ./initvals -f ar9003-2p2 | sha1sum
0ceddb5cf66737610fb51f04cf3e9ff71870c7b4  -

Cc: stable@kernel.org
Cc: Yixiang Li <yixiang.li@atheros.com>
Cc: Don Breslin <don.breslin@atheros.com>
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

0dfa6dbb

15 6月, 2010 1 次提交

ath9k_hw: update 5 GHz tx gain tables for femless and high power PA · 1cc5c4b5

由 Luis R. Rodriguez 提交于 6月 12, 2010

This updates the initvals for AR9003 to adjust the 5 GHz tx gain
tables for femless and high power PA.

References:

	Osprey 2.0 header file ver 72
	Osprey 2.2 header file ver 20

Checksums:

$ ./initvals -f ar9003-2p0
0x00000000c2bfa7d5        ar9300_2p0_radio_postamble
0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p0
0x00000000e0bc2c84        ar9300Modes_fast_clock_2p0
0x00000000056eaf74        ar9300_2p0_radio_core
0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p0
0x0000000078658fb5        ar9300_2p0_mac_postamble
0x0000000023235333        ar9300_2p0_soc_postamble
0x0000000054d41904        ar9200_merlin_2p0_radio_core
0x00000000748572cf        ar9300_2p0_baseband_postamble
0x000000009aa5a0a4        ar9300_2p0_baseband_core
0x000000003dffa526        ar9300Modes_high_power_tx_gain_table_2p0
0x000000001cfda724        ar9300Modes_high_ob_db_tx_gain_table_2p0
0x0000000011302700        ar9300Common_rx_gain_table_2p0
0x00000000e3eab114        ar9300Modes_low_ob_db_tx_gain_table_2p0
0x00000000c9d66d40        ar9300_2p0_mac_core
0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p0
0x00000000a0c54980        ar9300_2p0_soc_preamble
0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p0
0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p0
0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p0

$ ./initvals -f ar9003-2p2
0x00000000c2bfa7d5        ar9300_2p2_radio_postamble
0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e0bc2c84        ar9300Modes_fast_clock_2p2
0x00000000056eaf74        ar9300_2p2_radio_core
0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p2
0x0000000078658fb5        ar9300_2p2_mac_postamble
0x0000000023235333        ar9300_2p2_soc_postamble
0x0000000054d41904        ar9200_merlin_2p2_radio_core
0x000000008475a084        ar9300_2p2_baseband_postamble
0x000000009aaafd90        ar9300_2p2_baseband_core
0x000000003dffa526        ar9300Modes_high_power_tx_gain_table_2p2
0x000000001cfda724        ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000011302700        ar9300Common_rx_gain_table_2p2
0x00000000a9a2b114        ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000a9d66d40        ar9300_2p2_mac_core
0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a0c531c8        ar9300_2p2_soc_preamble
0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p2
0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p2
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

1cc5c4b5

03 6月, 2010 1 次提交

ath9k_hw: add support for the AR9003 2.2 · 7284635d

由 Luis R. Rodriguez 提交于 5月 12, 2010

The checksums of the initvals are:

initvals -f ar9003-2p2
0x00000000c2bfa7d5        ar9300_2p2_radio_postamble
0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p2
0x00000000e0bc2c84        ar9300Modes_fast_clock_2p2
0x00000000056eaf74        ar9300_2p2_radio_core
0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p2
0x0000000078658fb5        ar9300_2p2_mac_postamble
0x0000000023235333        ar9300_2p2_soc_postamble
0x0000000054d41904        ar9200_merlin_2p2_radio_core
0x000000008475a084        ar9300_2p2_baseband_postamble
0x000000009aaafd90        ar9300_2p2_baseband_core
0x000000003df9a326        ar9300Modes_high_power_tx_gain_table_2p2
0x000000001cfba124        ar9300Modes_high_ob_db_tx_gain_table_2p2
0x0000000011302700        ar9300Common_rx_gain_table_2p2
0x00000000a9a2b114        ar9300Modes_low_ob_db_tx_gain_table_2p2
0x00000000a9d66d40        ar9300_2p2_mac_core
0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p2
0x00000000a0c531c8        ar9300_2p2_soc_preamble
0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p2
0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p2
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

7284635d

12 5月, 2010 1 次提交

ath9k_hw: new initialization values for AR9003 · 7fca8e26

由 Luis R. Rodriguez 提交于 5月 10, 2010

These changes include:

  * For PAPRD, the TXRF3.capdiv5G, TXRF3.rdiv5G and TXRF3.rdiv2G
    are set to 0x0, the TXRF6.capdiv2G is set to 0x2 for all
    three chains.
  * The d2cas5G/d3cas5G/d4cas5G was updated to 4/4/4 in lowest_ob_db
    Tx gain table.
  * To improve DPPM, three parameters were updated (Released from Madhan):
	1. RANGE_OSDAC is set to 0x1 for 2G, 0x0 for 5G
	2. offsetC1 is set to 0xc
	3. inv_clk320_adc is set to 0x1
  * To reduce PHY error(from spur), cycpwr_thr1 and cycpwr_thr1_ext
    are increased to 0x8 at 2G.
  * The 2G Rx gain tables are updated with mixer gain setting 3,1,0.

The new checksums yield:

initvals -f ar9003
0x00000000c2bfa7d5        ar9300_2p0_radio_postamble
0x00000000ada2b114        ar9300Modes_lowest_ob_db_tx_gain_table_2p0
0x00000000e0bc2c84        ar9300Modes_fast_clock_2p0
0x00000000056eaf74        ar9300_2p0_radio_core
0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p0
0x0000000078658fb5        ar9300_2p0_mac_postamble
0x0000000023235333        ar9300_2p0_soc_postamble
0x0000000054d41904        ar9200_merlin_2p0_radio_core
0x00000000748572cf        ar9300_2p0_baseband_postamble
0x000000009aa5a0a4        ar9300_2p0_baseband_core
0x000000003df9a326        ar9300Modes_high_power_tx_gain_table_2p0
0x000000001cfba124        ar9300Modes_high_ob_db_tx_gain_table_2p0
0x0000000011302700        ar9300Common_rx_gain_table_2p0
0x00000000e3eab114        ar9300Modes_low_ob_db_tx_gain_table_2p0
0x00000000c9d66d40        ar9300_2p0_mac_core
0x000000001e1d0800        ar9300Common_wo_xlna_rx_gain_table_2p0
0x00000000a0c54980        ar9300_2p0_soc_preamble
0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p0
0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p0
0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p0

Cc: Don Breslin <don.breslin@atheros.com>
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

7fca8e26

08 5月, 2010 1 次提交

ath9k_hw: Update initvals for AR9003 for xb113 · bc6fb356

由 Luis R. Rodriguez 提交于 5月 06, 2010

Generated using the new shiny intivals-tool [1]:

initvals -w -f ar9003 > ar9003_initvals.h

The respective checksums are:

0x000000005a76829d        ar9300_2p0_radio_postamble
0x000000009d90cb74        ar9300Modes_lowest_ob_db_tx_gain_table_2p0
0x00000000e0bc2c84        ar9300Modes_fast_clock_2p0
0x00000000852fca34        ar9300_2p0_radio_core
0x0000000000000000        ar9300Common_rx_gain_table_merlin_2p0
0x0000000078658fb5        ar9300_2p0_mac_postamble
0x0000000023235333        ar9300_2p0_soc_postamble
0x0000000054d41904        ar9200_merlin_2p0_radio_core
0x00000000618455d4        ar9300_2p0_baseband_postamble
0x000000009aa590a4        ar9300_2p0_baseband_core
0x000000004783d946        ar9300Modes_high_power_tx_gain_table_2p0
0x000000006681db44        ar9300Modes_high_ob_db_tx_gain_table_2p0
0x000000001f318700        ar9300Common_rx_gain_table_2p0
0x000000009990cb74        ar9300Modes_low_ob_db_tx_gain_table_2p0
0x00000000c9d66d40        ar9300_2p0_mac_core
0x0000000039139500        ar9300Common_wo_xlna_rx_gain_table_2p0
0x00000000a0c54980        ar9300_2p0_soc_preamble
0x00000000292e2544        ar9300PciePhy_pll_on_clkreq_disable_L1_2p0
0x000000002d3e2544        ar9300PciePhy_clkreq_enable_L1_2p0
0x00000000293e2544        ar9300PciePhy_clkreq_disable_L1_2p0

[1] http://wireless.kernel.org/en/users/Drivers/ath9k_hw/initvals-tool

Cc: Tom Hammel <thammel@atheros.com>
Cc: Enis Akay <Enis.Akay@Atheros.com>
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

bc6fb356

28 4月, 2010 1 次提交

ath9k_hw: update initvals for AR9003 · 2fcb9131

由 Felix Fietkau 提交于 4月 26, 2010

This synchs up the initvals to the values used on the
Atheros HAL for AR9003. This specific change adds support
for a new high power module.
Signed-off-by: NFelix Fietkau <nbd@openwrt.org>
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

2fcb9131

17 4月, 2010 1 次提交

ath9k_hw: add initvals for the AR9003 hardware family · 13ce3e99

由 Luis R. Rodriguez 提交于 4月 15, 2010

The AR9003 hardware family now initializes hardware by block
components and into stages: pre, core and init.
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>

13ce3e99