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  1. 13 12月, 2006 2 次提交
  3. 08 12月, 2006 1 次提交
  5. 06 12月, 2006 1 次提交
  7. 04 12月, 2006 1 次提交
    • L
      [ARM] 3881/4: xscale: clean up cp0/cp1 handling · afe4b25e
      由 Lennert Buytenhek 提交于 
      XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Acked-by: NDan Williams <dan.j.williams@intel.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      afe4b25e
  9. 30 11月, 2006 2 次提交
  11. 15 10月, 2006 1 次提交
  13. 09 10月, 2006 1 次提交
    • D
      IRQ: Use the new typedef for interrupt handler function pointers · 40220c1a
      由 David Howells 提交于 
      Use the new typedef for interrupt handler function pointers rather than
actually spelling out the full thing each time.  This was scripted with the
following small shell script:

#!/bin/sh
egrep -nHrl -e 'irqreturn_t[ 	]*[(][*]' $* |
while read i
do
    echo $i
    perl -pi -e 's/irqreturn_t\s*[(]\s*[*]\s*([_a-zA-Z0-9]*)\s*[)]\s*[(]\s*int\s*,\s*void\s*[*]\s*[)]/irq_handler_t \1/g' $i || exit $?
done
Signed-Off-By: NDavid Howells <dhowells@redhat.com>
      40220c1a
  15. 07 10月, 2006 1 次提交
  17. 04 10月, 2006 2 次提交
  19. 02 10月, 2006 1 次提交
  21. 28 9月, 2006 1 次提交
    • D
      USB: pxa2xx_udc understands GPIO based VBUS sensing · b2bbb20b
      由 David Brownell 提交于 
      This updates the PXA 25x UDC board-independent infrastructure for VBUS sensing
and the D+ pullup.  The original code evolved from rather bizarre support on
Intel's "Lubbock" reference hardware, so that on more sensible hardware it
doesn't work as well as it could/should.

The change is just to teach the UDC driver how to use built-in PXA GPIO pins
directly.  This reduces the amount of board-specfic object code needed, and
enables the use of a VBUS sensing IRQ on boards (like Gumstix) that have one.
With VBUS sensing, the UDC is unclocked until a host is actually connected.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b2bbb20b
  23. 27 8月, 2006 1 次提交
  25. 02 8月, 2006 1 次提交
  27. 03 7月, 2006 1 次提交
  29. 02 7月, 2006 1 次提交
  31. 01 7月, 2006 1 次提交
  33. 29 6月, 2006 3 次提交
  35. 25 6月, 2006 1 次提交
  37. 21 6月, 2006 1 次提交
  39. 20 6月, 2006 4 次提交
  41. 18 6月, 2006 1 次提交
  43. 09 6月, 2006 1 次提交
  45. 06 6月, 2006 1 次提交
  47. 18 5月, 2006 1 次提交
  49. 06 5月, 2006 1 次提交
  51. 19 4月, 2006 1 次提交
  53. 03 4月, 2006 1 次提交
  55. 01 4月, 2006 3 次提交
  57. 29 3月, 2006 1 次提交
  59. 28 3月, 2006 1 次提交