According to the recent i.MX6 Quad technical reference manual, mode 0x4 (100b)
of the CCM_CS2DCR register (address 0x020C402C) bits [11-9] and [14-12] select
the PLL3 clock, and not the PLL3 PFD1 540M clock. In our code, the PLL3 root
clock is named 'pll3_usb_otg', select this instead of the 540M clock.
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver.  However, the commit
bd603455 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree.  It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.

 smp_twd: clock not found -2
 ...
 Calibrating local timer... 396.13MHz.

Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We always boot from PLL1, so let's have pll1_sys in the clks_init_on
list to have clk prepare/enable use count match the hardware status,
so that drivers managing pll1_sys like cpufreq can get the use count
right from the start.
Reported-by: NDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This mxs usbphy is only needs to be on after system boots
up, and software never needs to control it anymore.
Meanwhile, usbphy's parent needs to be notified if usb
is suspend or not. So we design below mxs usbphy usage:

- usbphy1_gate and usbphy2_gate:
Their parents are dummy clock, we only needs to enable
it after system boots up.
- usbphy1 and usbphy2
Usage reserved bit for this clock, in that case, the refcount
will be updated, but without hardware changing.
Signed-off-by: NPeter Chen <peter.chen@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add WAIT mode (ARM core clock gating) support to imx6q cpuidle driver.
As WAIT mode is broken on imx6q TO 1.0 and 1.1, it only enables the
support for revision 1.2 with chicken bit set.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

imx6q_clock_map_io() becomes an empty function since imx6q clock driver
is moved to common clock framework.  It's used nowhere now.  Remove it.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The hardware reset value of bit CCM_CLPCR_LPM enables WAIT mode
(WAIT_UNCLOCKED) by default.  However this is undesirable because
WAIT mode should only be enabled when there is a driver managing
ARM clock gating.  Correct the initial power mode to WAIT_CLOCKED
(disable WAIT mode).  While at it, the power mode after resuming
is also set back to WAIT_CLOCKED from STOP_POWER_OFF.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz
and has different outputs. Only the enet reference clock is implemented. This
patch changes the PLL so that it outputs 500MHz and adds the additional outputs
as dividers. This now matches the datasheet which says:

> This PLL synthesizes a low jitter clock from 24 MHz reference clock.
> The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are:
>  • Ref_PCIe = 125 MHz
>  • Ref_SATA = 100 MHz
>  • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

In recent reference manuals the PLLs were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

This adds the mmdc_ch1 as a possible parent for the ldb_di clk.
According to the datasheet, this clock can be selected at this mux.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>

It enables cpufreq support for imx6q with generic cpufreq-cpu0 driver.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Rename mach-imx/include/mach/common.h to mach-imx/common.h and update
all users to include common.h rather than mach/common.h.

It also removes an unneeded inclusion to common.h in
mach-imx/devices/devices.c.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The gpmi-nand driver can support the ONFI nand chip's EDO (extra data out)
mode in the asynchrounous mode. In the asynchrounous mode 5, the gpmi
needs 100MHz clock for the IO. But with the pll2_pfd0_352m, we can not
get the 100MHz clock.

So choose pll2_pfd2_396m as enfc_sel's parent.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It really becomes an maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.

Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx6q client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The ldb_di[01]_podf is implemented as a clk-divider that
divides by 1 or 2. In reality, the ldb_di[01]_ipu_div
dividers divide by either 3.5 or 7. Adding a fixed factor
of 1/3.5 fixes their children's clock rates.

This should probably be converted to rate table based dividers,
once available.

Cc: <stable@vger.kernel.org>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add clocks for gpmi-nand.
Signed-off-by: NHuang Shijie <shijie8@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There are a number of clkdev lookups left over from commit b0286f20
(ARM: imx6q: prepare and enable init on clks directly instead of
clk_get first), remove them since they are not needed now.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

add clock for apbh-dma.
Signed-off-by: NHuang Shijie <shijie8@gmail.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

When moving to common clk framework, the imx6q clks rom and mmdc_ch1_axi
get different on/off states than old clk driver, which breaks suspend
function.  There might be a better way to manage these clocks, but let's
takes the old clk driver approach to fix the regression first.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This also removes the usboh3 clk from the initially turned on
clocks which leaked in from an internal development tree.
Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

As the timer code now does a clk_get to get its clock we don't
need the struct clk argument anymore.
This also changes the alternative EPIT timer to do a clk_get.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It's used by audio drivers.
Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

It has been pointed out by device tree maintainer for several times
that the generic names 'serial' and 'ethernet' should be used for
those devices per ePAPR.  Renames imx uart and fec device tree nodes
to stop them being bad examples.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>