1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized  CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.

Here is the corresponding code which describe it.
+       int align = ~(line_length - 1);
+       end = ((end & align) == end) ? end - line_length : end & align;

a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Show cache line length in /proc/cpuinfo.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Copy & paste error.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch fix consistent code which had problems with consistent_free
function.
I am not sure if we need to call flush_tlb_all after it but it keeps
tlbs synced.
I added noMMU and MMU version together.

Uncached shadow feature is not tested.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Current implementation doesn't handle dcache_line_length
correctly that's why is better to use generic memcpy.

Cache optimized function could be good way howto improve
performance but must be based on benchmarking not blind
function like this.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Fix divide exception message to say "divide by zero".
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Cc:	Michal Simek <monstr@monstr.eu>
Cc:	microblaze-uclinux@itee.uq.edu.au
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I found several function which we don't use that's why I am removing them.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

_start is located in .text, which causes mismatch warnings with
machine_early_init() and start_kernel() in .init.text.
Signed-off-by: NSteven J. Magnani <steve@digidescorp.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Function traces on Microblaze don't include IRQ entry and exit arrows,
i.e.

 0)               |                            memcpy_toiovec() {
 0)   ==========> |
 0)               |                              do_IRQ() {
 ...
 0)   <========== |
 0) ! 5414.000 us |                            }

...because do_IRQ() doesn't have the proper attributes.
Signed-off-by: NSteven J. Magnani <steve@digidescorp.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Patch b3c1e01a should do it.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The Microblaze dynamic ftrace code assumes a call ordering that is not met
in all scenarios. Specifically, executing a command similar to:

  echo 105 > /sys/kernel/debug/tracing/set_ftrace_pid

before any other tracing-related commands results in a kernel panic:

  BUG: failure at arch/microblaze/kernel/ftrace.c:198/ftrace_update_ftrace_func()!

Recoding ftrace_update_ftrace_func() to use &ftrace_caller directly eliminates
the need to capture its address elsewhere (and thus rely on a particular call
sequence).
Signed-off-by: NSteven J. Magnani <steve@digidescorp.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

If early printk console is not enabled then all messages
are written to log buffer.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I forget to change register name in comments.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

TLB size was hardcoded in asm code. This patch brings ability
to change TLB size only in one place. (mmu.h).
Signed-off-by: NMichal Simek <monstr@monstr.eu>

On the base on GCOV analytics is helpful to add likely/unlikely
macros.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Cachegrind analysis need this fix to be able to log asm functions.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Sync labels.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

RESR and REAR uses the same regs in whole file.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This change synchronize register usage in code.
ESR = R4
EAR = R3
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Any sync branch must follow mts instructions not mfs.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Disable debug option in asm code.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

When the system has no lmb bram, main memory should be start from
zero because of microblaze vectors.

DTS fragment could look like:
	DDR2_SDRAM: memory@0 {
		device_type = "memory";
		reg = < 0x0 0x10000000 >;
	} ;

Then you have to setup CONFIG_KERNEL_BASE_ADDR=0 which caused
that kernel physical start address will be zero. On reset vector place
will be jump to 0x100 and on 0x100 starts kernel text.

You have to solve how to load the kernel before cpu starts.
Tested with XMD.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I would like to use asm-generic uaccess.h where are segment
macros defined. This is just first step.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

The "kstack=" command line parameter is not parsed correctly.
All proper values are interpreted as zero.
Signed-off-by: NSteven J. Magnani <steve@digidescorp.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h

percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>

Use the generic ptrace_resume code for PTRACE_SYSCALL, PTRACE_CONT and
PTRACE_KILL.  This also makes PTRACE_SINGLESTEP return -EIO while it
previously succeeded despite not actually causing any kind of single
stepping.

Also the TIF_SYSCALL_TRACE thread flag is now cleared on PTRACE_KILL which
it previously wasn't which is consistent with all architectures using the
modern ptrace code.
Signed-off-by: NChristoph Hellwig <hch@lst.de>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Roland McGrath <roland@redhat.com>
Acked-by: NMichal Simek <monstr@monstr.eu>
Cc: John Williams <john.williams@petalogix.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Use ptrace_request() in the three remaining architectures that didn't use it
(m68knommu, h8300, microblaze).  This means:

 - ptrace_request now handles PTRACE_{PEEK,POKE}{TEXT,DATA} and PTRACE_DETATCH
   calls that were previously called directly, or in case of h8300 even open
   coded.
 - adds new support for PTRACE_SETOPTIONS/PTRACE_GETEVENTMSG/
   PTRACE_GETSIGINFO/PTRACE_SETSIGINFO
Signed-off-by: NChristoph Hellwig <hch@lst.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Acked-by: NRoland McGrath <roland@redhat.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

Signed-off-by: NMichal Simek <monstr@monstr.eu>

There is possible to save r3/r4 at the beggining of user part
before calling handlers and at the end restore it.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

We have to use consistent code to be able to do coherent dma
function. In consistent code is used cache inhibit page mapping.
Xilinx reported that there is bug in Microblaze for WB and
d-cache_always use option. Microblaze 7.30.a should be first version
where is this bug removed.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

It is default option but both options must be measured.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I found several problems for ll_temac driver and on system with WB.
This early fix should fix it. I will clean this patch before I will add
it to mainline
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Signed-off-by: NFrans Pop <elendil@planet.nl>
Cc: microblaze-uclinux@itee.uq.edu.au
Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

For copy was used r7 register when CONFIG_CMDLINE_BOOL option
is enabled. But r7 stores pointer to fdt that's why machine_early_init
not detect compiled-in DTB.

I also moved kernel PID setup to have TLB init in one block
Signed-off-by: NMichal Simek <monstr@monstr.eu>

I found several problems for ll_temac driver and on system with WB.
This early fix should fix it. I will clean this patch before I will add
it to mainline
Signed-off-by: NMichal Simek <monstr@monstr.eu>

It is better to have init cache handling on one place.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch add core PREEMPT support for Microblaze.
I tried to trace it via tracers and I was able to see any output.

I also added low level debug functions to see if that code is called.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch is based on powerpc patch
64f16502

We did some cleanups and removed powerpc parts.
There is one new debug early listing function too.

Exclude function is only in Debug options.

We tested in on custom board.
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Support function for PCI. We don't use any advance mapping mechanism
that's why implementation is simple.
Signed-off-by: NMichal Simek <monstr@monstr.eu>