No one of supported MIPS machines has an IOMMU unit, so we can safely define
PCI_DMA_BUS_IS_PHYS = 1. Also remove iommu flag from the pci controller
structure, since it is useless.
Signed-off-by: NSergey Ryazanov <ryazanov.s.a@gmail.com>
Cc: Linux MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7604/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

SEGBITS is 40 bits or more, depending on CPU type.  Introduces optional
support for 48 bits of application virtual address space.  Only 16K and
64K pages are supported.

Enabling will result in a memory overhead of a small number of pages for
small applications.  For 64K pages a 3rd level of page tables is required
which has some impact during software TLB refill.

[ralf@linux-mips.org: Fixed things raised in the review of the version
posted and changed kconfig to be a bit more userfriendly.]
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: aleksey.makarov@auriga.com
Cc: james.hogan@imgtec.com
Cc: paul.burton@imgtec.com
Cc: david.daney@cavium.com
Cc: peterz@infradead.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: davidlohr@hp.com
Cc: kirill@shutemov.name
Cc: akpm@linux-foundation.org
Cc: mingo@kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10051/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

MIPS32 o32 ABI sigaction() processing on MIPS64 n64 kernel was incorrectly
set to processing aka rt_sigaction() variant only.
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: paul.burton@imgtec.com
Cc: richard@nod.at
Cc: luto@amacapital.net
Cc: alex.smith@imgtec.com
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: mpe@ellerman.id.au
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11321/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

MIPS hardware may have an antialising support and it works even
page size is small.

Setup a shared memory aliasing mask to page size if hardware has
an antialising support. Big shared memory mask forces a disruption
in page address assignment and that corrupts Android library memory
handling.
Signed-off-by: NLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: cernekee@gmail.com
Cc: paul.gortmaker@windriver.com
Cc: kumba@gentoo.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11516/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

flags is indeed unused.
Signed-off-by: NTony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11699/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1,
Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB,
L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local
register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast
TLB refill support, etc.

This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to
enable those enhancements which are not probed at run time. If you want
a generic kernel to run on all Loongson 3 machines, please say 'N'
here. If you want a high-performance kernel to run on new Loongson 3
machines only, please say 'Y' here.

Some additional explanations:
1) SFB locates between core and L1 cache, it causes memory access out
   of order, so writel/outl (and other similar functions) need a I/O
   reorder barrier.
2) Loongson 3 has a bug that di instruction can not save the irqflag,
   so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected
   by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di
   at all.
3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so
   MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12755/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this
is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which
can be used for fast TLB refill.

[ralf@linux-mips.org: Resolve conflict.]
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12754/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Loongson-2 has a 4 entry itlb which is a subset of jtlb, Loongson-3 has
a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. We should
write diag register to invalidate itlb/dtlb when flushing jtlb because
itlb/dtlb are not totally transparent to software.

For Loongson-3A R2 (and newer), we should invalidate ITLB, DTLB, VTLB
and FTLB before we enable/disable FTLB.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12753/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Loongson-3 maintains cache coherency by hardware, this means:
 1) It's icache is coherent with dcache.
 2) It's dcaches don't alias (maybe depend on PAGE_SIZE).
 3) It maintains cache coherency across cores (and for DMA).

So we can skip most cache flush operations by setting relevant handlers
to `cache_noop' in `r4k_cache_init'.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12752/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Loongson-3 CPU family:

Code-name       Brand-name       PRId
Loongson-3A R1  Loongson-3A1000  0x6305
Loongson-3A R2  Loongson-3A2000  0x6308
Loongson-3B R1  Loongson-3B1000  0x6306
Loongson-3B R2  Loongson-3B1500  0x6307

Features of R2 revision of Loongson-3A:

  - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache).
  - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is
     64 bytes.
  - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way
     set-associative).
  - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/
     Execute-Inhibit.

[ralf@linux-mips.org: Resolved merge conflicts.]
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12751/
Patchwork: https://patchwork.linux-mips.org/patch/13136/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs
handled in the same dispatching. This can speedup interrupt processing.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Steven J . Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12891/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

SB700/SB710/SB800 chipset ACPI code is mostly Loongson-3 specific
routines rather than a "platform driver".
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <sjhill@realitydiluted.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11273/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Strip some comments which probably meant to repeat the same value of the
define; they also contained a confusing 0x0x prefix.
Signed-off-by: NAntonio Ospite <ao2@ao2.it>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12254/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The files watch.c and ptrace.c contain various magic masks for
WatchLo/WatchHi register fields. Add some definitions to mipsregs.h for
these registers and make use of them in both watch.c and ptrace.c,
hopefully making them more readable.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Reviewed-by: NDavid Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12729/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

do_watch() clears bit 22 of cause without using a CAUSEF_* definition
from mipsregs.h. Add a definition for this bit (CAUSEF_WP) and make use
of it. Also use clear_c0_cause() instead of manual read/modify/write.
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12728/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

IS_ERR_VALUE macro should be used only with unsigned long type.
Specifically it works incorrectly with longer types.

The patch follows conclusion from discussion on LKML [1][2].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2120927
[2]: http://permalink.gmane.org/gmane.linux.kernel/2150581

[ralf@linux-mips.org: While it may not immediately be obvious, the type
of st_value in the end is an unsigned long equivalent so the invocation
of IS_ERR_VALUE() was valid but I'm applying the patch anyway for
clarity.]
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12553/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Propagate sNaN payload in quieting in the legacy-NaN mode as well.  If
clearing the quiet bit would produce infinity, then set the next lower
trailing significand field bit, matching the SB-1 and BMIPS5000 hardware
implementations.  Some other MIPS FPU hardware implementations do
produce the default qNaN bit pattern instead.

This reverts some changes made for semantics preservation with commit
dc3ddf42 [MIPS: math-emu: Update sNaN quieting handlers], consequently
bringing back most of the semantics from before commit fdffbafb [Lots of
FPU bug fixes from Kjeld Borch Egevang.], except from the qNaN produced
in the infinity case.  Previously the default qNaN bit pattern was
produced in that case.
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11483/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Update the ELF personality macros used for individual ABIs to make
actions in the same order across all of them and match formatting too.
Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Since commit 8cb48fe1 ("MIPS: Provide correct siginfo_t.si_stime"),
MIPS' uapi/asm/siginfo.h has included uapi/asm-generic/siginfo.h
directly before defining MIPS' struct siginfo, in order to get the
necessary definitions needed for the siginfo struct without the generic
copy_siginfo() hitting compiler errors due to struct siginfo not yet
being defined.

Now that the generic copy_siginfo() is moved out to linux/signal.h we
can safely include asm-generic/siginfo.h before defining the MIPS
specific struct siginfo, which avoids the uapi/ include as well as
breakage due to generic copy_siginfo() being defined before struct
siginfo.
Reported-by: NChristopher Ferris <cferris@google.com>
Fixes: 8cb48fe1 ("MIPS: Provide correct siginfo_t.si_stime")
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Petr Malat <oss@malat.biz>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.0-
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

octeon_smp_setup and octeon_prepare_cpus are just used during initialization
period, so mark them as __init. And, octeon_prepare_cpus is just used in smp.c,
so make it static as well.
Signed-off-by: NYang Shi <yang.shi@windriver.com>
Cc: david.daney@cavium.com
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12574/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Remove unneeded leds0 alias.
- Switch to bcm6345-l1-intc interrupt controller.
- Use interrupt-controller instead of periph_intc and cpu_intc.
- Add uart1 node.
- Single ohci and ehci nodes.
- Avoid using underscores in node names.
- Rename uart aliases to serial.
- Remove blank line in cpus node.

[ralf@linux-mips.org: fix references in bcm96368mvwg.dts so the file keeps
building.]
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Cc: robh@kernel.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Remove unneeded leds0 alias.
- Switch to bcm6345-l1-intc interrupt controller.
- Use interrupt-controller instead of periph_intc and cpu_intc.
- Add uart1, ehci and ohci nodes.
- Refactor syscon and syscon-reboot.
- Avoid using underscores in node names.
- Rename uart aliases to serial.
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Cc: robh@kernel.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13043/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This SoC is very similar to BCM63168 and Broadcom usually refers to them as
BCM63268.
Add BCM63268 and missing BCM63168 to device tree documentation.
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: f.fainelli@gmail.com
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Cc: robh@kernel.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13042/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This adds a device tree example for SFR Neufbox4 (Sercomm version), which
also serves as a real example for brcm,bcm6358-leds.
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: f.fainelli@gmail.com
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Cc: robh@kernel.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13041/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

BCM6358 has a shared TLB which conflicts with current SMP support, so it must
be disabled for now.
BCM6358 uses >= 0xfffe0000 addresses for internal registers, which need to be
remapped (by using a simplified version of BRCM63xx ioremap.h).
However, 0xfff80000 is a better address, since it also covers BCM3368, leaving
the possibility to add it in the future.
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jogo@openwrt.org
Cc: cernekee@gmail.com
Cc: robh@kernel.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13040/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Just to ease debugging of multiplatform kernel, make sure we print
"Broadcom BMIPS5200" for the BMIPS5200 implementation instead of
Broadcom BMIPS5000.

Fixes: 68e6a783 ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13014/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

BMIPS_GENERIC being multiplatform and intended to support BMIPS3200,
BMIPS3300, BMIPS4350, BMIPS4380 and BMIPS5000-class processors, there is
not much more we can put in there since they do not share the same I and
D cache line sizes at all (doubled for every new generation
essentially), some processors have a S-cache, some don't, some have a
FPU, some don't.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13013/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

local_r4k___flush_cache_all() is missing a special check for BMIPS5000
processors, we need to blast the S-cache, just like other MTI processors
since we have an inclusive cache. We also need an additional __sync() to
make sure this is completed.

Fixes: d74b0172 ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13012/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

BMIPS5000 and BMIPS5200 processor have no D cache aliases, and this is
properly handled by the per-CPU override added at the end of
r4k_cache_init(), the problem is that the output of probe_pcache()
disagrees with that, since this is too late:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes

With the change moved earlier, we now have a consistent output with the
settings we are intending to have:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, no aliases, linesize 32 bytes

Fixes: d74b0172 ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13011/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

BMIPS5000 and BMIPS52000 processors have their I-cache filling from the
D-cache. Since BMIPS_GENERIC does not provide (yet) a
cpu-feature-overrides.h file, this was not set anywhere, so make sure
the R4K cache detection takes care of that.

Fixes: d74b0172 ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13010/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Enable CONFIG_MTD_BCM63XX_PARTS in arch/mips/configs/bmips_be_defconfig
since this is a necessary option to parse the built-in flash partition
table on BMIPS big-endian SoCs (Cable Modem and DSL).
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12256/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Enable CONFIG_MTD_BCM63XX_PARTS in arch/mips/configs/bcm63xx_defconfig
since this is a necessary option to parse the built-in flash partition
table on BCM63xx SoCs.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Cc: simon@fire.lp0.eu
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12255/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Add DMA device
- Add NAND device
- Add GPIO device
- Add LED device
- Update the defconfig and rename it to loongson1b_defconfig
- Fix ioremap size
- Other minor fixes
Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: dmaengine@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/13033/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Fixes wrong bcm7425 SATA AHCI hardware interrupt property value with
periph_intc and SATA PHY unit address, and removes needless
brcm,broken-{ncq,phy} properties what are not used anywhere.
Signed-off-by: NJaedon Shin <jaedon.shin@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Dragan Stancevic <dragan.stancevic@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/13017/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add UART, I2C, SATA device tree nodes on Broadcom BCM7xxx MIPS-based
platforms.
Signed-off-by: NJaedon Shin <jaedon.shin@gmail.com>
Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Dragan Stancevic <dragan.stancevic@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/13016/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

In Kconfig "=n" is not correct syntax, "!" is the preferred way for
false-positive expression.
Signed-off-by: NYang Shi <yang.shi@windriver.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12572/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

When debugging a relocated kernel, the addresses of the relocated
symbols and the offset applied is essential information. If the kernel
is compiled with debugging information, then print this information
during bootup using the same function as the panic notifier.

[ralf@linux-mips.org: Fixed spelling mistake pointed out by
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>.]
Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
Cc: Aaro Koskinen <aaro.koskinen@nokia.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Cc: Jaedon Shin <jaedon.shin@gmail.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: kernel-hardening@lists.openwall.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12989/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds KASLR to the MIPS kernel.

Entropy is derived from the banner, which will change every build and
random_get_entropy() which should provide additional runtime entropy.
Additionally the bootloader may pass entropy via the /chosen/kaslr-seed
node in device tree.

The kernel is relocated by up to RANDOMIZE_BASE_MAX_OFFSET bytes from
its link address (PHYSICAL_START). Because relocation happens so early
in the kernel boot, the amount of physical memory has not yet been
determined. This means the only way to limit relocation within the
available memory is via Kconfig.
Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: kernel-hardening@lists.openwall.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12990/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Early access to the kernel command line requires early access to the FDT
for platforms which pass the command line within the device tree. There
was no common way to retrieve the location of the FDT without incurring
side effects, such as plat_mem_setup which, on Malta at least,
initializes a bunch of other stuff.

This patch adds plat_get_ftd() for IMG platforms.
Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: kernel-hardening@lists.openwall.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12988/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add option to KConfig to enable the kernel to relocate itself at
runtime.

Relocation is supported R2 and later of the MIPS architecture, 32bit
and 64bit. The platform is also required to provide support through
plat_get_fdt() added in a later patch.
Signed-off-by: NMatt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: kernel-hardening@lists.openwall.com
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12987/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>