This is moving core clock and clock gating init for Kirkwood to its
own file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This is moving core clock and clock gating init for Dove to its own
file and adds a Kconfig option. Also init functions are added and
declared so they get called on of_clk_init.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Based on the current common functions for core clocks and clock
gating control, new common functions are joined in a single file.
Given the opportunity, names of functions and structs are unified,
and also a Kconfig entry is added.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Clock gates found on MVEBU SoCs get registered by a common function.
To allow specific SoCs to provide tweaks introduce flags to the clock
gate descriptor instead of filling up the common function SoC specific
tweaks.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The current revision of the datasheet only mentions the gatable clocks
for the PCIe 0.0, 0.1, 0.2 and 0.3 interfaces, and forgot to mention
the ones for the PCIe 1.0, 1.1, 1.2, 1.3, 2.0 and 3.0
interfaces. After confirmation with Marvell engineers, this patch adds
the missing gatable clocks for those PCIe interfaces.

It also changes the name of the previously existing PCIe gatable
clocks, in order to match the naming using the datasheets.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

The Armada 370 has two gatable clocks for each PCIe interface, and we
want both of them to be enabled. We therefore make one of the two
clocks a child of the other, as we did for the sataX and sataXlnk
clocks on Armada XP.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

cpu_freq_select is used as array subscript, thus the valid value range
is 0 ... ARRAY_SIZE() - 1.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up trivial merge issues]

The use common of_clk_init() function simplifies the clock initialization
and adds handling of the DT "fixed-clock".
Signed-off-by: NJean-Francois Moine <moinejf@free.fr>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed $SUBJECT to reflect correct file path]

Correct spelling typo in various drivers.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJiri Kosina <jkosina@suse.cz>

The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The
CPU can either use the a high speed cpu clock, or the slower DDR
clock. Add a driver to swap between these two clock sources.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

the variable cpuclk and clk_name should be properly freed when error happens.
Signed-off-by: NCong Ding <dinggnu@gmail.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

If the Orion WDT driver is built as a module, an opps occurs during
clk lookup when calling mvebu_clk_gating_get_src().  Remove the
inappropriate __init tag so the function is available for modules
after kernel init.
Signed-off-by: NJoshua Coombs <josh.coombs@gmail.com>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>

This driver allows to provide DT clocks for clock gates found on
Marvell Dove and Kirkwood SoCs. The clock gates are referenced by
the phandle index of the corresponding bit in the clock gating control
register to ease lookup in the datasheet.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Add Armada 370/XP specific CPU clocks
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.

Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>