- 06 1月, 2011 1 次提交
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由 Dan Carpenter 提交于
"info->cmdset" gets dereferenced in __readid() so it needs to be initialized earlier in the function. This bug was introduced in 18c81b18 "mtd: pxa3xx_nand: remove the flash info in driver structure". Cc: stable@kernel.org [2.6.37+] Reported-and-tested-by: NSven Neumann <s.neumann@raumfeld.com> Signed-off-by: NDan Carpenter <error27@gmail.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 25 10月, 2010 4 次提交
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由 Lei Wen 提交于
For different command need different oob requirement, set the proper oob length by different cmd. Signed-off-by: NLei Wen <leiwen@marvell.com> Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Lei Wen 提交于
After probe, all info already transfer to driver structure. There is no need to keep the original flash info. So that we could safely free the flash info in memory, which may grows larger when more flash is suported. Signed-off-by: NLei Wen <leiwen@marvell.com> Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Lei Wen 提交于
We certainly don't need to send read id command times by times, since we already know what the id is after the first read id... So create a default timing which could ensure it would successfully read id out all supported chip. Then follow the build-in table to reconfigure the timing. Signed-off-by: NLei Wen <leiwen@marvell.com> Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Lei Wen 提交于
Adding a new flash definition would need less code. Keep the platform passing flash definition method. If one flash is both defined in platform data and builtin table, driver would select the one from platform data first. By this way, platform could select the timing most suit for itself, not need to follow the common settings. Signed-off-by: NLei Wen <leiwen@marvell.com> Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 13 9月, 2010 1 次提交
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由 Mark F. Brown 提交于
Signed-off-by: NMark F. Brown <mark.brown314@gmail.com> Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 18 8月, 2010 1 次提交
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由 Axel Lin 提交于
Test on a PXA310 platform with Samsung K9F2G08X0B NAND flash, with tCH=5 and clk is 156MHz, ns2cycle(5, 156000000) returns -1. ns2cycle returns negtive value will break NDTR0_tXX macros. After checking the commit log, I found the problem is introduced by commit 5b0d4d7c "[MTD] [NAND] pxa3xx: convert from ns to clock ticks more accurately" To get num of clock cycles, we use below equation: num of clock cycles = time (ns) / one clock cycle (ns) + 1 We need to add 1 cycle here because integer division will truncate the result. It is possible the developers set the Min values in SPEC for timing settings. Thus the truncate may cause problem, and it is safe to add an extra cycle here. The various fields in NDTR{01} are in units of clock ticks minus one, thus we should subtract 1 cycle then. Thus the correct equation should be: num of clock cycles = time (ns) / one clock cycle (ns) + 1 - 1 = time (ns) / one clock cycle (ns) Signed-off-by: NAxel Lin <axel.lin@gmail.com> Signed-off-by: NLei Wen <leiwen@marvell.com> Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com> Cc: stable@kernel.org
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- 10 5月, 2010 1 次提交
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由 Marc Kleine-Budde 提交于
The pxa32xx_nand driver doesn't support partition tables from the command line. This patch adds support for it. Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 30 3月, 2010 1 次提交
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由 Tejun Heo 提交于
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: NTejun Heo <tj@kernel.org> Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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- 01 12月, 2009 8 次提交
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由 Haojian Zhuang 提交于
Since the same nand controller is shared between ARCH_PXA and ARCH_MMP. Move the pxa3xx_nand.h from mach directory to plat directoy. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Cc: David Woodhouse <david.woodhouse@intel.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
Support samsung 2GbX8 and 32GbX8 nand flash. Support micron 4GbX8 and 4GbX16 nand flash. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
In some bootloader, IRQ is enabled. Writing nand triggers unexpected interrupts. So disable nand irq in initialization. After nand initialized and in working state, irq is controlled by nand driver. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
Nand driver uses IRQ_NAND as hardcode irq number. In ARCH_MMP, the irq number is different. So get irq resource from platform device structure and use it in initialization and deinitialization code. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
Although nand controller is same between PXA3xx and MMP, the register space is different. Remove the hardcode register address setting in pxa3xx_nand.h. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
Slow down the tRp of Micron NAND flash timing. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
Initialize the read buffer content to 0xFF. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Haojian Zhuang 提交于
When fetch nand data with non-DMA mode, we should align info->data_size to 32bit, not 8bit. Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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- 30 11月, 2009 1 次提交
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由 David Hunter 提交于
The shift operator used here to convert from bytes to 32-bit words is backwards. Signed-off-by: NDavid Hunter <hunterd42@gmail.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 20 9月, 2009 1 次提交
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由 Yeasah Pell 提交于
Acked-by: NEric Miao <eric.y.miao@gmail.com> Signed-off-by: NYeasah Pell <yeasah@comrex.com> Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 21 3月, 2009 3 次提交
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由 Mike Rapoport 提交于
Signed-off-by: NMike Rapoport <mike@compulab.co.il> Acked-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mike Rapoport 提交于
Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Mike Rapoport 提交于
Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 09 3月, 2009 1 次提交
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由 Eric Miao 提交于
1. Driver code where pxa_request_dma() is called will most likely reference DMA registers as well, and it is really unnecessary to include pxa-regs.h just for this. Move the definitions into <mach/dma.h> and make relevant drivers include it instead of <mach/pxa-regs.h>. 2. Introduce DMAC_REGS_VIRT as the virtual address base for these DMA registers. This allows later processors to re-use the same IP while registers may start at different I/O address. Signed-off-by: NEric Miao <eric.miao@marvell.com>
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- 05 1月, 2009 2 次提交
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由 Matt Reimer 提交于
The various fields in NDTR{01} are in units of clock ticks minus one, but the ns2cycle macro mistakenly adds one, inflating the number of clock ticks and making it impossible to set any of these fields to zero. Signed-off-by: NMatt Reimer <mreimer@vpop.net> Signed-off-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Matt Reimer 提交于
Reads from non-page-aligned addresses were broken because while the address to read from was correctly written to NDCB*, a full page was always read. Fix this by ignoring the column and only using the page address. I suspect this whole-page behavior is due to the controller's need to read the entire page in order to generate correct ECC. In the non-ECC case this could be optimized to use the column address, and to set the read length to what is being requested rather than the length of an entire page. Signed-off-by: NMatt Reimer <mreimer@vpop.net> Signed-off-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 03 12月, 2008 1 次提交
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由 Denis V. Lunev 提交于
STM 2Gb flash is a large-page NAND flash. Set operations accordingly. This field is dereferenced without a check in several places resulting in OOPS. Signed-off-by: NDenis V. Lunev <den@openvz.org> Acked-by: NEric Miao <ymiao3@marvell.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 02 12月, 2008 1 次提交
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由 Eric Miao 提交于
Where 'pxa_dma_desc' and 'pxa_{request,free}_dma' are referenced. Signed-off-by: NEric Miao <eric.miao@marvell.com>
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- 27 11月, 2008 1 次提交
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由 Russell King 提交于
Where devices only have one consumer, passing a consumer clock ID has no real benefit. Remove it. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 02 9月, 2008 6 次提交
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由 Enrico Scholz 提交于
Minor patch to help debugging of NAND detection. Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Enrico Scholz 提交于
This patch moves some attributes out from the platform data into the dynamically created nand device. This results into a cleaner interface and allows to use constant pxa3xx_nand_flash definitions. Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Enrico Scholz 提交于
This patch marks some attributes as 'const' which are set only once and never be modified by the driver. There are some changes in parameter list and variable declarations too which mark them as 'const'. Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Enrico Scholz 提交于
This patch adds a MTD_NAND_PXA3xx_BUILTIN configuration variables which allows to disable usage of builtin flash-type table. Not enabling this option saves some space in the generated driver. Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Enrico Scholz 提交于
This patch adds 'flash' and 'num_flash' attributes to the platform data. There was added code in the driver to iterate across these attributes in the detect-flash routine. This is done similarly to the existing method which uses a 'builtin_flash_types' field. Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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由 Enrico Scholz 提交于
This patch moves the exported datastructures from the pxa3xx_nand.c driver into the <mach/pxa3xx_nand.h> header. This is a plain movement without any modification of the attributes. This is the first one of a set of patches which: * allows to specify used NAND flash in the platform code and allows to turn off the old way to specify NAND characteristics in the driver. This way did not worked well as these characteristics depend on the platform and can not be derived from NAND id alone. E.g. some NAND chips share the same ID (e.g. K9K8G08U0A and K9NBG08U5A) but have different timings (which are written in the common driver currently and must be modified there). * adds 'const' annotations at various places Further patches will be sent to the mtd-list. Signed-off-by: NEnrico Scholz <enrico.scholz@sigma-chemnitz.de> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 01 9月, 2008 1 次提交
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由 Semun Lee 提交于
Signed-off-by: NSemun Lee <semun.lee@samsung.com> Acked-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
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- 07 8月, 2008 1 次提交
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由 Russell King 提交于
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 6月, 2008 1 次提交
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由 Eric Miao 提交于
Signed-off-by: NEric Miao <eric.miao@marvell.com> Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
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- 23 4月, 2008 2 次提交
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由 David Woodhouse 提交于
Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
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由 eric miao 提交于
This is preliminary since: 1. It supports only _one_ chip select at the moment. As there is no existing platforms available using two chip selects of the NAND controller, it shall really not include code for supporting the 2nd chip select for now, as such code cannot be verified. 2. It resorts to the default and simpliest memory based badblock table 3. Only limited types of nand flash are currently supported. Most PXA3xx processors come with on-chip NAND flash dies, so there isn't much flexibility for other types of NAND. 4. The NAND controller should be configured to detect the device's ID, thus making it difficult to use nand_scan_ident() to assist the detection process (though it's not impossible) TODO: fix all the above limitations of cuz :-) Signed-off-by: Neric miao <eric.miao@marvell.com> Cc: Sergey Podstavin <spodstavin@ru.mvista.com> Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
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