Moreover, report hardware page table walker support as 'htw' in the ASE
list of /proc/cpuinfo, if the core implements this feature.
Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7334/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch is prepared for Loongson's NUMA support, it offer meaningful
sysfs files such as physical_package_id, core_id, core_siblings and
thread_siblings in /sys/devices/system/cpu/cpu?/topology.
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Reviewed-by: NAndreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/7184/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Reverts commit 795038a6 because
d6d3c9af provides the same functionality
in a more generic way.  Both patches applied however means that the
VPE and TC IDs get printed twice currently.

And there are more CPUs or configurations that want to provide special
per-CPU information in /proc/cpuinfo.  So I think there needs to be a
hook mechanism, such as a notifier.

This is a first cut only; I need to think about what sort of looking
the notifier needs to have.  But I'd appreciate testing on MT hardware!
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6066/

Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>

This patch adds support for probing the MSAP bit within the Config3
register in order to detect the presence of the MSA ASE. Presence of the
ASE will be indicated in /proc/cpuinfo. The value of the MSA
implementation register will be displayed at boot to aid debugging and
verification of a correct setup, as is done for the FPU.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6430/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Currently the supported ISA is only printed on the latest architectures.
Print it also on legacy platforms.
Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6295/

Add support for including VPE and TC ids in /proc/cpuinfo output as
appropriate when MT/SMTC is enabled.
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Signed-off-by: NMarkos Chandras <markos.chandras@imgtec.com>
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6065/

MIPS I is the ancestor of all MIPS ISA and architecture variants.  Anything
ever build in the MIPS empire is either MIPS I or at least contains MIPS I.
If it's running Linux, that is.

So there is little point in having cpu_has_mips_1 because it will always
evaluate as true - though usually only at runtime.  Thus there is no
point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it.

Little complication: traps.c was using a test for a pure MIPS I ISA as
a test for an R3000-style cp0.  To deal with that, use a check for
cpu_has_3kex or cpu_has_4kex instead.

cpu_has_3kex is a new macro.  At the moment its default implementation is
!cpu_has_4kex but this may eventually change if Linux is ever going to
support the oddball MIPS processors R6000 and R8000 so users of either
of these macros should not make any assumptions.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5551/

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This adds the option to build the Linux kernel using only the
microMIPS ISA. The resulting kernel binary is, at a minimum,
20% smaller than using the MIPS32R2 ISA.
Signed-off-by: NSteven J. Hill <Steven.Hill@imgtec.com>

Previously this functionality was only available to users of the mips_machine
api. Moving the code to prom.c allows us to also add a OF wrapper.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5164/

There is a missing " " inside /proc/cpuinfo.

The bad commit was:
commit a96102be
Author: Steven J. Hill <sjhill@mips.com>
Date:   Fri Dec 7 04:31:36 2012 +0000
MIPS: Add printing of ISA version in cpuinfo.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4988/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The presence of the MIPS Virtualization Application-Specific Extension
is indicated by CP0_Config3[23].  Probe for this and report it in
/proc/cpuinfo.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4904/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4682/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Display the MIPS ISA version release in the /proc/cpuinfo file.

[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions.  Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.

Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it.  For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code.  The same for a 32-bit kernel running on a 64-bit processor.  This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The number of %s was just getting ridiculous.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo.  The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This has been obsolescent for a while; time for the final push.

In adjacent context, replaced old cpus_* with cpumask_*.
Signed-off-by: NRusty Russell <rusty@rustcorp.com.au>
Acked-by: David S. Miller <davem@davemloft.net> (arch/sparc)
Acked-by: Chris Metcalf <cmetcalf@tilera.com> (arch/tile)
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: linux-hexagon@vger.kernel.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Helge Deller <deller@gmx.de>
Cc: sparclinux@vger.kernel.org

Probe c0_config4 for KScratch registers and report them in /proc/cpuinfo.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1877/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch adds a generic solution to support multiple machines based on
a given SoC within a single kernel image. It is implemented already for
several other architectures but MIPS has no generic support for that yet.

[Ralf: This competes with DT but DT is a much more complex solution and this
code has been used by OpenWRT for a long time so for now DT is a bad reason
to stop the merge but longer term this should be migrated to DT.]
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: kaloz@openwrt.org
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1814/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

They tend to get not updated when files are moved around or copied and
lack any obvious use.  While at it zap some only too obvious comments and
as per Shinya's suggestion, add a copyright header to extable.c.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
Acked-by: NShinya Kuribayashi <shinya.kuribayashi@necel.com>
Acked-by: NThadeu Lima de Souza Cascardo <cascardo@holoscopio.com>

Outlining fixes the issue were on certain CPUs such as the R10000 family
the delay loop would need an extra cycle if it overlaps a cacheline
boundary.

The rewrite also fixes build errors with GCC 4.4 which was changed in
way incompatible with the kernel's inline assembly.

Relying on pure C for computation of the delay value removes the need for
explicit.  The price we pay is a slight slowdown of the computation - to
be fixed on another day.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

It should print the type of the Nth processor.
Signed-off-by: NJohannes Dickgreber <tanzy@gmx.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Probe for watch register characteristics, and report them in /proc/cpuinfo.
Signed-off-by: NDavid Daney <ddaney@avtrex.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NJan Engelhardt <jengelh@computergmbh.de>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

So far /proc/cpuinfo has been the only user but human readable processor
name are more useful than that for proc.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.
    
It originally comes from the OpenWrt patches.
    
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NFuxin Zhang <zhangfx@lemote.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Make sure cpu_has_fpu (which uses smp_processor_id()) is used only in
atomic context.
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Currently, /proc/cpuinfo contains several copies of the information for
whatever processor we happen to be scheduled on. This patch makes it contain
the proper information for each CPU, which is particularly useful on mixed
R12k/R10k IP27 machines.
Signed-off-by: NKarl-Johan Karlsson <creideiki@lysator.liu.se>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NJörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: NAdrian Bunk <bunk@stusta.de>

Signed-off-by: NJoshua Kinard <kumba@gentoo.org>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

    
Nothing exciting; Linux just didn't know it yet so this is most adding
a value to a case statement.
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>