- 30 11月, 2006 2 次提交
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由 Russell King 提交于
Fix warnings and errors in arch/arm/mm for nommu build. Remove commented out function prototype in pgtable-nommu.h Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
These files want to provide/access ELF hwcap information, so should be including asm/elf.h rather than asm/procinfo.h Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 23 11月, 2006 1 次提交
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由 Dan Williams 提交于
/* * Note: Drivers should NOT use this function directly, as it will break * platforms with CONFIG_DMABOUNCE. * Use the driver DMA support - see dma-mapping.h (dma_sync_*) */ Signed-off-by: NDan Williams <dan.j.williams@intel.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 08 11月, 2006 1 次提交
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由 Ray Lehtiniemi 提交于
show_mem() was not correctly handling holes in the memory map. It was treating the freed sections of the map as though they contained valid struct page entries. This could cause incorrect debugging output or even a kernel panic. This patch keeps the struct meminfo around after system initialization so that show_mem() can use it when scanning memory. show_mem() now walks over each bank of each online node, rather than assuming that each node contains a single contiguous bank. Signed-off-by: NRay Lehtiniemi <rayl@mail.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 11月, 2006 1 次提交
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由 Paul Gortmaker 提交于
ARM patch 3756/1 added HWCAP_IWMMXT. This patch adds support for broadcasting that info via /proc/cpuinfo and sets it for the CPU features of the PXA270. I've booted 19rc3 on a pxa270 and confirmed that the /proc/cpuinfo shows "iwmmxt" in the Features. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: NNicolas Pitre <nico@cam.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 09 10月, 2006 1 次提交
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由 Al Viro 提交于
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 30 9月, 2006 3 次提交
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由 Russell King 提交于
XIP kernels need to know the start/end of text, but we were missing the declaration of _etext in mmu.c. Add it. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Sukadev Bhattiprolu 提交于
This is an updated version of Eric Biederman's is_init() patch. (http://lkml.org/lkml/2006/2/6/280). It applies cleanly to 2.6.18-rc3 and replaces a few more instances of ->pid == 1 with is_init(). Further, is_init() checks pid and thus removes dependency on Eric's other patches for now. Eric's original description: There are a lot of places in the kernel where we test for init because we give it special properties. Most significantly init must not die. This results in code all over the kernel test ->pid == 1. Introduce is_init to capture this case. With multiple pid spaces for all of the cases affected we are looking for only the first process on the system, not some other process that has pid == 1. Signed-off-by: NEric W. Biederman <ebiederm@xmission.com> Signed-off-by: NSukadev Bhattiprolu <sukadev@us.ibm.com> Cc: Dave Hansen <haveblue@us.ibm.com> Cc: Serge Hallyn <serue@us.ibm.com> Cc: Cedric Le Goater <clg@fr.ibm.com> Cc: <lxc-devel@lists.sourceforge.net> Acked-by: NPaul Mackerras <paulus@samba.org> Signed-off-by: NAndrew Morton <akpm@osdl.org> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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由 Jason Baron 提交于
Make PROT_WRITE imply PROT_READ for a number of architectures which don't support write only in hardware. While looking at this, I noticed that some architectures which do not support write only mappings already take the exact same approach. For example, in arch/alpha/mm/fault.c: " if (cause < 0) { if (!(vma->vm_flags & VM_EXEC)) goto bad_area; } else if (!cause) { /* Allow reads even for write-only mappings */ if (!(vma->vm_flags & (VM_READ | VM_WRITE))) goto bad_area; } else { if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } " Thus, this patch brings other architectures which do not support write only mappings in-line and consistent with the rest. I've verified the patch on ia64, x86_64 and x86. Additional discussion: Several architectures, including x86, can not support write-only mappings. The pte for x86 reserves a single bit for protection and its two states are read only or read/write. Thus, write only is not supported in h/w. Currently, if i 'mmap' a page write-only, the first read attempt on that page creates a page fault and will SEGV. That check is enforced in arch/blah/mm/fault.c. However, if i first write that page it will fault in and the pte will be set to read/write. Thus, any subsequent reads to the page will succeed. It is this inconsistency in behavior that this patch is attempting to address. Furthermore, if the page is swapped out, and then brought back the first read will also cause a SEGV. Thus, any arbitrary read on a page can potentially result in a SEGV. According to the SuSv3 spec, "if the application requests only PROT_WRITE, the implementation may also allow read access." Also as mentioned, some archtectures, such as alpha, shown above already take the approach that i am suggesting. The counter-argument to this raised by Arjan, is that the kernel is enforcing the write only mapping the best it can given the h/w limitations. This is true, however Alan Cox, and myself would argue that the inconsitency in behavior, that is applications can sometimes work/sometimes fails is highly undesireable. If you read through the thread, i think people, came to an agreement on the last patch i posted, as nobody has objected to it... Signed-off-by: NJason Baron <jbaron@redhat.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Hugh Dickins <hugh@veritas.com> Cc: Roman Zippel <zippel@linux-m68k.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: NAndi Kleen <ak@muc.de> Acked-by: NAlan Cox <alan@lxorguk.ukuu.org.uk> Cc: Arjan van de Ven <arjan@linux.intel.com> Acked-by: NPaul Mundt <lethal@linux-sh.org> Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp> Cc: Ian Molton <spyro@f2s.com> Signed-off-by: NAndrew Morton <akpm@osdl.org> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 29 9月, 2006 2 次提交
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由 Hyok S. Choi 提交于
In nommu mode, the exception vector location depends on the platforms. Some of the implementations may have some special exception control forwarding method in their ROM/flash and for some of them has its own re-mapping mechanism by the h/w. This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default. This feature depends on CP15 and does not supported by ARM740. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a dummy abort handler which returns zero for the base restored Data Abort model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up for the base updated Data Abort model cores. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 9月, 2006 8 次提交
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由 Russell King 提交于
Don't offer non-MMU based CPUs for selection when CONFIG_MMU is set. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM946E-S core support which has typically 8KB I&D cache. It has a MPU and supports ARMv5TE instruction set. Because the ARM946E-S core can be synthesizable with various cache size, CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache and a MPU. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM9TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
This patch adds ARM7TDMI core support which has no cache and no CP15 register(no memory control unit). Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Hyok S. Choi 提交于
By merging of uClinux/ARM, we need to treat various CPU cores which have MMU, MPU or even none for memory management. The memory management coprocessors are controlled by CP15 register set and the ARM core family can be categorized by 5 groups by the register ; G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022, v6 and the derivations sa1100, sa110, xscale, xsc3. G-b. CP15 is MPU : 740, 940, 946, 996, 1156. G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design) G-d. CP15 is exist, but nothing for memory managemnt : 966, 968. G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the family can be defined as : - CPU_CP15 only : G-d - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable) - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable) - !CPU_CP15 : G-e Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 27 9月, 2006 7 次提交
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由 Russell King 提交于
Since do_bad_area() always takes the currently active task and (supposed to) take the currently active MM, there's no point passing them to this function. Instead, obtain references to them inside do_bad_area(). Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Add an empty setup_mm_for_reboot() function for nommu machines. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
mm-armv.c now only contains the pgd allocation/freeing code, so rename it to have a more sensible filename. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
If we're going to have mmu.c for code which is specific to the MMU machines, we might as well move the other MMU initialisation specific code from mm-armv.c into this new file. This also allows us to make some functions static. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Move the MMU specific code from init.c into mmu.c, and add nommu fixups to nommu.c Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
nommu does not require the page table manipulation code in the bootmem initialisation paths. Move this into separate inline functions. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 George G. Davis 提交于
The ARM XIP_KERNEL map created in devicemaps_init() is wrong. The map.pfn is rounded down to an even 1MiB section boundary which results in va/pa translations errors when XIP_PHYS_ADDR starts on an odd 1MiB boundary and this causes the kernel to hang. This patch fixes ARM XIP_KERNEL translation errors for the odd 1MiB XIP_PHYS_ADDR boundary case. Signed-off-by: NGeorge G. Davis <gdavis@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 26 9月, 2006 1 次提交
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由 Dave McCracken 提交于
One of the changes necessary for shared page tables is to standardize the pxx_page macros. pte_page and pmd_page have always returned the struct page associated with their entry, while pte_page_kernel and pmd_page_kernel have returned the kernel virtual address. pud_page and pgd_page, on the other hand, return the kernel virtual address. Shared page tables needs pud_page and pgd_page to return the actual page structures. There are very few actual users of these functions, so it is simple to standardize their usage. Since this is basic cleanup, I am submitting these changes as a standalone patch. Per Hugh Dickins' comments about it, I am also changing the pxx_page_kernel macros to pxx_page_vaddr to clarify their meaning. Signed-off-by: NDave McCracken <dmccr@us.ibm.com> Cc: Hugh Dickins <hugh@veritas.com> Signed-off-by: NAndrew Morton <akpm@osdl.org> Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
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- 25 9月, 2006 4 次提交
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由 George G. Davis 提交于
Fix thinko in the flush_ptrace_access() "if (expr)" for the ARM VIPT non-aliasing cache case. We only need to flush cache when VM_EXEC is set in vma->vm_flags but "if (expr) always evaluates to true on UP systems for the ARM VIPT non-aliasing cache case. Signed-off-by: NGeorge G. Davis <gdavis@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Lennert Buytenhek 提交于
Split the iop3xx mach type into iop32x and iop33x -- split the config symbols, and move the code in the mach-iop3xx directory to the mach-iop32x and mach-iop33x directories. Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Lennert Buytenhek 提交于
On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't clear the dirty bits, which means that if we invalidate a dirty line, the dirty data can still be written back to memory later on. To work around this, dma_inv_range() on these two processors is implemented as dma_flush_range() (i.e. do a clean D-cache line before doing the invalidate D-cache line.) For this, we currently have a processor ID check in xscale_dma_inv_range(), but a better solution is to add a separate cache_fns and proc_info for A0/A1 80200. Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Lennert Buytenhek 提交于
Prevent userland from mapping in physical address regions >= 4G by checking for that in valid_mmap_phys_addr_range(). Unfortunately, we cannot override valid_mmap_phys_addr_range() without also overriding valid_phys_addr_range(), so copy drivers/char/mem.c's version of valid_phys_addr_range() over to arch/arm/mm/mmap.c as well. Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 20 9月, 2006 2 次提交
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由 Russell King 提交于
Rename mmu.c to context.c - it's the ARMv6 ASID context handling code rather than generic "mmu" handling code. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Move top_pmd into arch/arm/mm/mm.h - nothing outside arch/arm/mm references it. Move the repeated definition of TOP_PTE into mm/mm.h, as well as a few function prototypes. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 15 9月, 2006 1 次提交
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由 Dan Williams 提交于
Patch from Dan Williams commit a6a38a66 changed the iop321 id to a value that does not work with all platforms. Change the mask to permit bit 11. Tested on an iq80321 600Mhz CRB. Signed-off-by: NDan Williams <dan.j.williams@intel.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 07 9月, 2006 1 次提交
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由 Catalin Marinas 提交于
Patch from Catalin Marinas The ARM926EJ-S CPU has the VFP coprocessor and therefore it should be shown in the /proc/cpuinfo if CONFIG_VFP is enabled. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 9月, 2006 1 次提交
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由 George G. Davis 提交于
Patch from George G. Davis Resolve ARM1136 VIPT non-aliasing cache coherency issues observed when using ptrace to set breakpoints and cleanup copy_{to,from}_user_page() while we're here as requested by Russell King because "it's also far too heavy on non-v6 CPUs". NOTES: 1. Only access_process_vm() calls copy_{to,from}_user_page(). 2. access_process_vm() calls get_user_pages() to pin down the "page". 3. get_user_pages() calls flush_dcache_page(page) which ensures cache coherency between kernel and userspace mappings of "page". However flush_dcache_page(page) may not invalidate I-Cache over this range for all cases, specifically, I-Cache is not invalidated for the VIPT non-aliasing case. So memory is consistent between kernel and user space mappings of "page" but I-Cache may still be hot over this range. IOW, we don't have to worry about flush_cache_page() before memcpy(). 4. Now, for the copy_to_user_page() case, after memcpy(), we must flush the caches so memory is consistent with kernel cache entries and invalidate the I-Cache if this mm region is executable. We don't need to do anything after memcpy() for the copy_from_user_page() case since kernel cache entries will be invalidated via the same process above if we access "page" again. The flush_ptrace_access() function (borrowed from SPARC64 implementation) is added to handle cache flushing after memcpy() for the copy_to_user_page() case. Signed-off-by: NGeorge G. Davis <gdavis@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 28 8月, 2006 1 次提交
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由 Lennert Buytenhek 提交于
Patch from Lennert Buytenhek On armv4t systems, we have always compiled the kernel with -march=armv4 instead of -march=armv4t, which means that any use of bx will bomb out. Commit ba9b5d76 introduced the use of bx in the kernel, which means we need to compile with -march=armv4t on armv4t systems now. Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 29 7月, 2006 3 次提交
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由 Catalin Marinas 提交于
Patch from Catalin Marinas This patch adds #ifdef around some variables in the arch/arm/mm/ioremap.c file. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 George G. Davis 提交于
Patch from George G. Davis As reported by various folks on the ARM Linux kernel mailing list, the video-buf.ko driver has undefined references on all ARM machines which use it as observed during `make modules`: Warning: "v4wb_clear_user_page" [drivers/media/video/video-buf.ko] undefined! Similar warnings exist for all ARM machines which use this driver. So this change adds the missing EXPORT_SYMBOLs to allow using this driver as a module. Signed-off-by: NGeorge G. Davis <gdavis@mvista.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Lennert Buytenhek 提交于
Patch from Lennert Buytenhek The IOP 80219 xscale CPU is a stripped down version of the IOP32x. But the fact that the 80219 and IOP32x are very similar doesn't mean that they need to share a cpu table entry. It's also somewhat confusing for the end user to see the 80219 reported as an IOP32x, so this patch splits the IOP32x cpu table entry to make a separate entry for the 80219. Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: NDan Williams <dan.j.williams@intel.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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