In PG2.0 there is an issue where PHY's FDSP Code RAM sometimes gets
corrupted when exiting from ELP mode. This issue is related to FDSP
Code RAM clock implementation.

PG2.1 introduces a HW fix for this issue that requires the driver to
change the FDSP Code Ram clock settings (mux it to ATGP clock instead
of its own clock).

This workaround uses PHY_FPGA_SPARE_1 register and is relevant to WL8
PG2.1 devices.

The fix is also backward compatible with older PG2.0 devices where the
register PHY_FPGA_SPARE_1 is not used and not connected.

The fix is done in the wl18xx_pre_upload function (must be performed
before uploading the FW code) and includes the following steps:

1. Disable FDSP clock
2. Set ATPG clock toward FDSP Code RAM rather than its own clock.
3. Re-enable FDSP clock
Signed-off-by: NYair Shapira <yair.shapira@ti.com>
Signed-off-by: NIdo Reis <idor@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

Print board type, PG with metal and ROM versions.
This might help debugging HW related issues.
Signed-off-by: NVictor Goldenshtein <victorg@ti.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

wl18xx_conf_phy represents part of the FW native wl18xx_mac_and_phy_params
structure. Remove it and replace the phy part of the wl18xx conf with the
FW bound structure. This allows us to set/override all members.

Increment the wlconf version to ensure compatibility with the new
structure
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

PG2 requires 4 new parameters that to be passed to the PHY.

Use the actual PHY initialization struct size for the mem size of the
PHY_INIT section, to account for additions in params.

[Make sure PG1 still gets the original struct - Arik]
Signed-off-by: NIdo Reis <idor@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

PG2 has a unique chip id. It supports similar HW quirks.
Signed-off-by: NIdo Reis <idor@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

Add the get_mac operation in order to fetch the BD_ADDR from fuse ROM,
so that we can derive the WLAN MAC addresses from it.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>

Add the correct FW name for PLT (which is the same as the normal
firmware) and implement the plt_init operation.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>

Add more board types and remove a now unneeded write to SCR_PAD2 setting
the board type.
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

Read the HW PG version of the 18xx chip from FUSE.

Based on an earlier patch by Luciano Coelho <coelho@ti.com>.
Signed-off-by: NArik Nemtsov <arik@wizery.com>
Signed-off-by: NLuciano Coelho <coelho@ti.com>

Instead of using hardcoded values for a single frequency, we need to
read the frequency and use the appropriate values for it in the top
initialization.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>

The firmware uses the SCR_PAD2 register to read the board type passed
from the driver.  The values don't match the ones used in the mac and
phy configuration, so we need to map them before writing.  This commit
adds a translation table that is used when writing the board type to
SCR_PAD2.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>

Add the operations that allow wlcore to trigger commands to the
firmware and acknowledge when an event has been fully received.

Allocate a private buffer to hold the maximum sized cmd. Send the
entire length of the buffer each time a command is sent to signal
EOT. Remove the previous EOT mechanism.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>

Implement the boot operation.  Add a wl18xx-specific configuration
structure (namely to configure the mac and phy parameters).

The default hw configuration matches the DVP board.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>

Add the register table with the appropriate values for wl18xx.
Signed-off-by: NLuciano Coelho <coelho@ti.com>
Signed-off-by: NArik Nemtsov <arik@wizery.com>