- 25 2月, 2012 2 次提交
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由 Alban Browaeys 提交于
Before loading the lut (gamma), check the active state of intel_crtc, otherwise at least on gen2 hang ensue. This is reproducible in Xorg via: xset dpms force off then xgamma -rgamma 2.0 # freeze. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44505Signed-off-by: NAlban Browaeys <prahal@yahoo.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Eugeni Dodonov 提交于
As noticed by Torsten Kaiser, the operator precedence can play tricks with us here. CC: Dave Airlie <airlied@redhat.com> Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 24 2月, 2012 2 次提交
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由 Hai Lan 提交于
When setting overlay position with x<0, it will divide 0 and make drm driver crash. Signed-off-by: NHai Lan <hai.lan@intel.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Dave Airlie 提交于
Booted my i965 machine and it started printing the unsupported pixel format of 0 message (once I added content to it). Oh looksie here, we pass 0. fix. v2: compile it. Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45966Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDave Airlie <airlied@redhat.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 16 2月, 2012 1 次提交
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由 Eugeni Dodonov 提交于
With base on latest findings, RC6p seems to be respondible for RC6-related issues on Sandy Bridge platform. To work-around those issues, the previous solution was to completely disable RC6 on Sandy Bridge for the past few releases, even if plain RC6 was not giving any issues. What this patch does is preventing RC6p from being enabled on Sandy Bridge even if users enable RC6 via a kernel parameter. So it won't change the defaults in any way, but will ensure that if users do enable RC6 manually it won't break their machines by enabling this extra state. Proper fix for this (enabling specific RC6 states according to the GPU generation) were proposed for the -next kernel, but we are too late in the release process now to pick such changes. Acked-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 11 2月, 2012 4 次提交
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由 Kenneth Graunke 提交于
The BSpec Workarounds page states that bits 10 and 26 must be set to avoid 3D ring hangs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Eugeni Dodonov 提交于
This adds the workaround for WaCatErrorRejectionIssue which could result in a system hang. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Eugeni Dodonov 提交于
This adds two cache-related workarounds for Ivy Bridge which can lead to 3D ring hangs and corruptions. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Eugeni Dodonov 提交于
This is yet another workaround related to clock gating which we need on Ivy Bridge. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKenneth Graunke <kenneth@whitecape.org> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 09 2月, 2012 1 次提交
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由 Keith Packard 提交于
An identical patch has been merged for i9xx_crtc_mode_set: Commit 59df7b17 Author: Christian Schmidt <schmidt@digadd.de> Date: Mon Dec 19 20:03:33 2011 +0100 drm/intel: Fix initialization if startup happens in interlaced mode [v2] But that one neglected to fix up the ironlake+ path. This should fix the issue reported by Alfonso Fiore where booting with only a HDMI cable connected to his TV failed to display anything. The issue is that the bios set up things for 1080i and used the pannel fitter to scale up the lower progressive resolutions. We failed to clear the interlace bit in the PIPEACONF register, resulting in havoc. v2: Be more paranoid and just unconditionally clear the field before setting new values. Cc: Peter Ross <pross@xvid.org> Cc: Alfonso Fiore <alfonso.fiore@gmail.com> Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 29 1月, 2012 1 次提交
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由 Daniel Vetter 提交于
An identical patch has been merged for i9xx_crtc_mode_set: Commit 59df7b17 Author: Christian Schmidt <schmidt@digadd.de> Date: Mon Dec 19 20:03:33 2011 +0100 drm/intel: Fix initialization if startup happens in interlaced mode [v2] But that one neglected to fix up the ironlake+ path. This should fix the issue reported by Alfonso Fiore where booting with only a HDMI cable connected to his TV failed to display anything. The issue is that the bios set up things for 1080i and used the pannel fitter to scale up the lower progressive resolutions. We failed to clear the interlace bit in the PIPEACONF register, resulting in havoc. Cc: Peter Ross <pross@xvid.org> Tested-by: NAlfonso Fiore <alfonso.fiore@gmail.com> Signed-Off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 28 1月, 2012 1 次提交
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由 Chris Wilson 提交于
Enabling FBC is causing the BLT ring to run between 10-100x slower than normal and frequently lockup. The interim solution is disable FBC once more until we know why. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 14 1月, 2012 1 次提交
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由 Jesse Barnes 提交于
We can call the plane init function unconditionally, but don't need to complain if it fails, since that will only happen if we're out of memory (and other things will fail) or if we're on the wrong platform (which is ok). And remove the DRM_ERRORs from the sprite code itself to avoid dmesg spam. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 13 1月, 2012 1 次提交
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由 Jesse Barnes 提交于
The transcoder port may changed from mode set to mode set, so make sure to mask out the selection bits before setting the right ones or we'll get black screens when going from transcoder B to A. Tested-by: NVincent Vanackere <vincent.vanackere@gmail.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 04 1月, 2012 6 次提交
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由 Jesse Barnes 提交于
If it failed, leave it in the "off" state. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
If a PCH pipe PLL is being used by transcoder C, don't disable it. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Eric Anholt 提交于
They don't fix our problems alone, but we're told to set them. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
The video sprites support various video surface formats natively and can handle scaling as well. So add support for them using the new DRM core sprite support functions. v2: use drm specific fourcc header and defines v3: address Daniel's comments: - don't take struct mutex around register access (only needed for regs in the GT power well) - don't hold struct mutex across vblank waits - fix up update_plane API (pass obj instead of GTT offset) - add interlaced defines for sprite regs - drop unnecessary 'reg' variables - comment double buffered reg flushing Also fix w/h confusion when writing the scaling reg. v4: more fixes, address more comments from Daniel, and include Hai's fix - prevent divide by zero in scaling calculation (Hai Lan) - update to Ville's new DRM_FORMAT_* types - fix sprite watermark handling (calc based on CRTC size, separate from normal display wm) - remove private refcounts now that the fb cleanups handles things v5: add linear surface support v6: remove color key clearing & setting from update_plane For this version, I tested DPMS since it came up in the last review; DPMS off/on works ok when a video player is working under X, but for power saving we'll probably want to do something smarter. I'll leave that for a separate patch on top. Likewise with the refcounting/fb layer handling, which are really separate cleanups. Reviewed-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
We learned that the ECOBUS register was inside the GT power well, and so *did* need force wake to be read, so it gets removed from the list of 'doesn't need force wake' registers. That means the code reading ECOBUS after forcing the mt_force_wake function to be called needs to use I915_READ_NOTRACE; it doesn't need to do more force wake fun as it's already done it manually. This also adds a comment explaining why the MT forcewake testing code only needs to call mt_forcewake_get/put and not disable RC6 manually -- the ECOBUS read will return 0 if the device is in RC6 and isn't using MT forcewake, causing the test to work correctly. Signed-off-by: NKeith Packard <keithp@keithp.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
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由 Ben Widawsky 提交于
This matches the modern specs more accurately. This will be used by the following patch to fix the way we display RC status. Signed-off-by: NBen Widawsky <ben@bwidawsk.net> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 27 12月, 2011 1 次提交
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由 Keith Packard 提交于
RC6 fails again. > I found my system freeze mostly during starting up X and KDE. Sometimes it > works for some minutes, sometimes it freezes immediatly. When the freeze > happens, everything is dead (even the reset button does not work, I need to > power cycle). > I disabled RC6, and my system runs wonderfully. > The system is a Z68 Pro board with Sandybridge i5-2500K processor, 8 > GB of RAM and UEFI firmware. Reported-by: NKai Krakow <hurikhan77@gmail.com> Signed-off-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 20 12月, 2011 5 次提交
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由 Ville Syrjälä 提交于
Otherwise each driver would need to keep the information inside their own framebuffer object structure. Also add offsets[]. BOs on the other hand are driver specific, so those can be kept in driver specific structures. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Christian Schmidt 提交于
My EFI BIOS starts the graphics card up in my projector's preferred EDID mode, 1080@60i. The Intel driver does not clear all the interlaced bits. This patch introduces a new PIPECONF_INTERLACE_MASK define and uses it to restore progressive mode. Signed-of-by: NChristian Schmidt <schmidt@digadd.de> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Wu Fengguang 提交于
The ELD may or may not change when switching the video mode. If unchanged, don't trigger hot plug events to HDMI audio driver. This avoids disturbing the user with repeated printks. Reported-by: NNick Bowler <nbowler@elliptictech.com> Signed-off-by: NWu Fengguang <fengguang.wu@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Wu Fengguang 提交于
Change the definitions from GEN5 to IBX as they aren't in the CPU and some SNB systems actually shipped with IBX chipsets (or, at least that's a supported configuration). The GEN7_* register addresses actually take effect since GEN6 and should be prefixed by CPT, the PCH code name. Suggested-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NWu Fengguang <fengguang.wu@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Wu Fengguang 提交于
SandyBridge should be using the same register addresses as IvyBridge. Signed-off-by: NWu Fengguang <fengguang.wu@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 17 12月, 2011 3 次提交
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由 Adam Jackson 提交于
Some active adaptors (VGA usually) only have two lanes at 2.7GHz. That's a maximum pixel clock of 144MHz at 8bpc, but 192MHz at 6bpc. Fixes Asus UX31 panel being black at startup due to no valid modes since dc22ee6f. v2: Rebased to current code, resulting in the fix applying to EDP panels as well. Also changed from spatio-temporal to just spatial dithering on pre-ironlake, to be conssitent (and less visual flicker) Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net> Tested-by: NEric Anholt <eric@anholt.net> Tested-by: NDirk Hohndel <hohndel@infradead.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
This fixes a race where we may try to finish a page flip and decrement the refcount even if our vblank_get failed and we ended up with a spurious flip pending interrupt. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=34211. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
RC6 should always work on IVB, and should work on SNB whenever IO remapping is disabled. RC6 never works on Ironlake. Make the default value for the parameter follow these guidelines. Setting the value to either 0 or 1 will force the specified behavior. Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NKenneth Graunke <kenneth@whitecape.org> Reviewed-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38567 Cc: Ted Phelps <phelps@gnusto.com> Cc: Peter <pab1612@gmail.com> Cc: Lukas Hejtmanek <xhejtman@fi.muni.cz> Cc: Andrew Lutomirski <luto@mit.edu>
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- 01 12月, 2011 1 次提交
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由 Ville Syrjälä 提交于
Name the formats as DRM_FORMAT_X instead of DRM_FOURCC_X. Use consistent names, especially for the RGB formats. Component order and byte order are now strictly specified for each format. The RGB format naming follows a convention where the components names and sizes are listed from left to right, matching the order within a single pixel from most significant bit to least significant bit. The YUV format names vary more. For the 4:2:2 packed formats and 2 plane formats use the fourcc. For the three plane formats the name includes the plane order and subsampling information using the standard subsampling notation. Some of those also happen to match the official fourcc definition. The fourccs for for all the RGB formats and some of the YUV formats I invented myself. The idea was that looking at just the fourcc you get some idea what the format is about without having to decode it using some external reference. Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 24 11月, 2011 1 次提交
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由 Keith Packard 提交于
On IVB C0+ with newer BIOSes, the forcewake handshake has changed. There's now a bitfield for different driver components to keep the GT powered on. On Linux, we centralize forcewake handling in one place, so we still just need a single bit, but we need to use the new registers if MT forcewake is enabled. This needs testing on affected machines. Please reply with your tested-by if you had problems after a BIOS upgrade and this patch fixes them. v2: force MT mode. shift by 16 v3: set MT force wake bits then check ECOBUS Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=42923Tested-by: NManoj Iyer <manoj.iyer@canonical.com> Tested-by: NRobert Hooker <robert.hooker@canonical.com> Tested-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 17 11月, 2011 1 次提交
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由 Keith Packard 提交于
PCH eDP has many of the same needs as regular PCH DP connections, including the DP_CTl bit settings, the TRANS_DP_CTL register. Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 16 11月, 2011 1 次提交
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由 Jesse Barnes 提交于
To properly support the various plane formats supported by different hardware, the kernel must know the pixel format of a framebuffer object. So add a new ioctl taking a format argument corresponding to a fourcc name from the new drm_fourcc.h header file. Implement the fb creation hooks in terms of the new mode_fb_cmd2 using helpers where the old bpp/depth values are needed. v2: create DRM specific fourcc header file for sharing with libdrm etc v3: fix rebase failure and use DRM fourcc codes in intel_display.c and update commit message v4: make fb_cmd2 handle field into an array for multi-object formats pull in Ville's fix for the memcpy in drm_plane_init apply Ville's cleanup to zero out fb_cmd2 arg in drm_mode_addfb v5: add 'flags' field for interlaced support (from Ville) Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com> Acked-by: NAlan Cox <alan@lxorguk.ukuu.org.uk> Reviewed-by: NRob Clark <rob.clark@linaro.org> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 08 11月, 2011 2 次提交
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由 Eric Anholt 提交于
Unlike the previous one, I don't have known testcases it fixes. I'd rather not go through the same debug cycle on whatever testcases those might be. Signed-off-by: NEric Anholt <eric@anholt.net> Cc: stable@kernel.org Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Eric Anholt 提交于
Fixes rendering failures in Unigine Tropics and Sanctuary and the mesa "fire" demo. Signed-off-by: NEric Anholt <eric@anholt.net> Cc: stable@kernel.org Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 29 10月, 2011 2 次提交
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由 Adam Jackson 提交于
Shouldn't hide these behind _DRIVER, they're all KMS-related. Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Daniel Vetter 提交于
<ajax> i'm getting tempted to just disable temporal <mjg59> Approved. <ajax> apparently it makes the screen look pulse-y which is worse than the disease. References: http://lists.freedesktop.org/archives/intel-gfx/2011-October/012545.htmlTested-by: NОлег Герман <oleg.german@gmail.com> Reviewed-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 21 10月, 2011 3 次提交
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由 Jesse Barnes 提交于
Belongs in PCH enable instead. The duplication is worrying and the specs explicitly list transcoder select *after* actual PLL enable, which doesn't occur until later. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
Just some extra debug output. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
The watermark reg for the third pipe is in an unusual offset; add support for it and set watermarks for 3 pipe configs. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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