The arch_timer_evtstrm_enable hooks in arm and arm64 are substantially
similar, the only difference being a CONFIG_COMPAT-conditional section
which is relevant only for arm64.  Copy the arm64 version to the
driver, removing the arch-specific hooks.
Signed-off-by: NNathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NWill Deacon <will.deacon@arm.com>

The only difference between arm and arm64's implementations of
arch_counter_set_user_access is that 32-bit ARM does not enable user
access to the virtual counter.  We want to enable this access for the
32-bit ARM VDSO, so copy the arm64 version to the driver itself, and
remove the arch-specific implementations.
Signed-off-by: NNathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NWill Deacon <will.deacon@arm.com>

The arm and arm64 VDSOs need CP15 access to the architected counter.
If this is unavailable (which is allowed by ARM v7), indicate this by
changing the clocksource name to "arch_mem_counter" before registering
the clocksource.

Suggested by Stephen Boyd.
Signed-off-by: NNathan Lynch <nathan_lynch@mentor.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NWill Deacon <will.deacon@arm.com>

According to HW spec, we have to disable the counter before setting
it, if we don't this, in pressure test, sometimes the timer might
not generate interrupt any more.

And this patch also fixes a typo for register set by changing 0x7
to 0x3. 0x7 is loop mode in HW, but here we are using oneshot 0x3.
Signed-off-by: NHao Liu <Hao.Liu@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

New TTCs support 32bit mode. Older versions support
only 16bit modes. Keep 16bit mode as default
and 32bit optional.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The clock is not unprepared in case of the request IRQ fails.

Also update to request_irq.
Signed-off-by: NGaël PORTAY <gael.portay@gmail.com>
Acked-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Currently we wait until both cp15 and mem timers are probed if we
have both timer device nodes present in the device tree without
checking if the device is actually available. If one of the timer
device node present is disabled, the system locks up on the boot
as no timer gets registered.

This patch adds the check for the availability of the timer device
so that unavailable timers are discarded correctly. It also adds
the missing of_node_put.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

In order to avoid waking up the system in a low power mode, the
clocksource should not generate interrupts anymore. Disable the PIT
timer interrupt when changing into the CLOCK_EVT_MODE_SHUTDOWN mode.

[dlezcano] : remove superfluous empty line
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NBill Pringlemeir <bpringlemeir@nbsps.com>

Meson6 SoCs are equipped with 5 32-bit timers, called TIMER_A, TIMER_B,
TIMER_C, TIMER_D and TIMER_E.

The driver is providing clocksource support for the 32-bit counter using
TIMER_E. Clockevents are also supported using TIMER_A.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NCarlo Caione <carlo@caione.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>

The MCT has a nice 64-bit counter.  That means that we _can_ register
as a 64-bit clocksource and sched_clock.  ...but that doesn't mean we
should.

The 64-bit counter is read by reading two 32-bit registers.  That
means reading needs to be something like:
- Read upper half
- Read lower half
- Read upper half and confirm that it hasn't changed.

That wouldn't be terrible, but:
- THe MCT isn't very fast to access (hundreds of nanoseconds).
- The clocksource is queried _all the time_.

In total system profiles of real workloads on ChromeOS, we've seen
exynos_frc_read() taking 2% or more of CPU time even after optimizing
the 3 reads above to 2 (see below).

The MCT is clocked at ~24MHz on all known systems.  That means that
the 32-bit half of the counter rolls over every ~178 seconds.  This
inspired an optimization in ChromeOS to cache the upper half between
calls, moving 3 reads to 2.  ...but we can do better!  Having a 32-bit
timer that flips every 178 seconds is more than sufficient for Linux.
Let's just use the lower half of the MCT.

Times on 5420 to do 1000000 gettimeofday() calls from userspace:
* Original code:                      1323852 us
* ChromeOS cache upper half:          1173084 us
* ChromeOS + ldmia to optimize:       1045674 us
* Use lower 32-bit only (this code):  1014429 us

As you can see, the time used doesn't increase linearly with the
number of reads and we can make 64-bit work almost as fast as 32-bit
with a bit of assembly code.  But since there's no real gain for
64-bit, let's go with the simplest and fastest implementation.

Note: with this change roughly half the time for gettimeofday() is
spent in exynos_frc_read().  The rest is timer / system call overhead.

Also note: this patch disables the use of the MCT on ARM64 systems
until we've sorted out how to make "cycles_t" always 32-bit.  Really
ARM64 systems should be using arch timers anyway.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Acked-by Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Using the __raw functions is discouraged.  Update the file to
consistently use the proper functions.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Add device-tree support to PXA platforms.
The driver still needs to maintain backward non device-tree
compatibility as well, which implies :
 - a non device-tree init function
 - a static registers base address in the driver
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Move time.c from arch/arm/mach-pxa/time.c to
drivers/clocksource/pxa_timer.c.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This adds the clocksource driver for Cirrus Logic CLPS711X series SoCs.
Designed primarily for migration CLPS711X subarch for multiplatform & DT,
for this as the "OF" and "non-OF" calls implemented.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

In the clocksource driver, we didn't explicitly enable the clock. it makes the
clk reference counter wrong. We didn't encounter any hang issue because the
tick's clock input has been open and is shared by some other hardware
components, but if we don't enable those components in kernel, in the stage of
disabling unused clk in kernel boot, Linux tick hangs.

This patch fixes it. it does an explicit prepare and enable to the clock input,
and increases the usage counter of the clk.
Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

In 'em_sti.c', it will call devm_ioremap_resource() which need
HAS_IOMEM. So need let EM_TIMER_STI depend on HAS_IOMEM, too.

The related error (with allmodconfig under score):

  LD      init/built-in.o
em_sti.c:(.text.em_sti_probe+0x84): undefined reference to `devm_ioremap_resource'
make: *** [vmlinux] Error 1
Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.

The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.

Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Purpose Timer block can be run with two clocks. A 13 MHz system
clock and the RTC clock running at 32 KHz. This implementation uses the system
clock with no clock source divider.

The interrupts are shared between the different timers and have to be read back
from a register. We just enable one interrupt for the clock event. The clock
event timer is used by all cores.
Signed-off-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

It should be "MTU2" instead of "TMU2"
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NWolfram Sang <wsa@sang-engineering.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

Ensure that platform maintainers check the CPU part number in the right
manner: the CPU part number is meaningless without also checking the
CPU implement(e|o)r (choose your preferred spelling!)  Provide an
interface which returns both the implementer and part number together,
and update the definitions to include the implementer.

Mark the old function as being deprecated... indeed, using the old
function with the definitions will now always evaluate as false, so
people must update their un-merged code to the new function.  While
this could be avoided by adding new definitions, we'd also have to
create new names for them which would be awkward.
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch registers the exynos mct clocksource as the current timer
as it has constant clock rate. This will generate correct udelay for
the exynos platform and avoid using unnecessary calibrated
jiffies. This change has been tested on exynos5420 based board and
udelay is very close to expected.

Without this patch udelay() on exynos5400 / exynos5800 is wildly
inaccurate due to big.LITTLE not adjusting loops_per_jiffy correctly.
Also without this patch udelay() on exynos5250 can be innacruate
during transitions between frequencies < 800 MHz (you'll go 200 MHz ->
800 MHz -> 300 MHz and will run at 800 MHz for a time with the wrong
loops_per_jiffy).

[dianders: reworked and created version 3]
Signed-off-by: NAmit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

In (93bfb769 clocksource: exynos_mct: register sched_clock callback) we
supported using the MCT as a scheduler clock.  We properly marked
exynos4_read_sched_clock() as notrace.  However, we then went and
called another function that _wasn't_ notrace.  That means if you do:

  cd /sys/kernel/debug/tracing/
  echo function_graph > current_tracer

You'll get a crash.

Fix this (but still let other readers of the MCT be trace-enabled) by
adding an extra function.  It's important to keep other users of MCT
traceable because the MCT is actually quite slow to access and we want
exynos4_frc_read() to show up in ftrace profiles if it's the
bottleneck.
Signed-off-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Document DT bindings and parse them in the MTU2 driver.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NWolfram Sang <wsa@sang-engineering.com>

Document DT bindings and parse them in the TMU driver.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Document DT bindings and parse them in the CMT driver.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

The global spinlock is used to protect the shared start/stop register.
Now that all MTU2 channels are handled by a single device instance, use
a per-device spinlock.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NWolfram Sang <wsa@sang-engineering.com>

Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NWolfram Sang <wsa@sang-engineering.com>

The global spinlock is used to protect the shared start/stop register.
Now that all TMU channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

The global spinlock is used to protect the shared start/stop register.
Now that all CMT channels are handled by a single device instance, use a
per-device spinlock.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Now that all platforms have switched to the new-style platform data,
drop support for the legacy version.
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NSimon Horman <horms+renesas@verge.net.au>

Move the clocksource Kconfig entries into their own menu, so that they
don't pollute the main device driver menu.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: http://lkml.kernel.org/r/20140616114845.343e9960@endymion.delvareSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

All Tegra SoCs have a freerunning microsecond counter which can be used as a
delay timer.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Unfortunately on some exynos systems, resetting the mct counter also
resets the architected timer counter.  This can cause problems if the
architected timer driver has already been initialized because the kernel
will think that the counter has wrapped around, causing a big jump in
printk timestamps and delaying any scheduled clock events until the
counter reaches the value it had before it was reset.

The kernel code makes no assumptions about the initial value of the mct
counter so there is no reason from a software perspective to clear the
counter before starting it.  This also fixes the problems described in
the previous paragraph.

Cc: Olof Johansson <olof@lixom.net>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NChirantan Ekbote <chirantan@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

The newly merged versatile sched clock support uses a deprecated
interface.  Of course that patch got routed through the ARM tree instead
of going through the relevant maintainer tree.

Use the proper interface so we can get rid of the cruft.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

The versatile express changes for 3.16 introduced a number of
build regressions for randconfig kernels by not tracking dependencies
between the components right.

This patch tries to rectify that:

* the mach-vexpress code cannot link without the syscfg driver,
  which in turn needs MFD_VEXPRESS_SYSREG
* various drivers call devm_regmap_init_vexpress_config(), which
  has to be exported so it can be used by loadable modules
* the configuration bus uses OF DT helper functions that are not
  available to platforms disable CONFIG_OF
* The sysreg driver exports GPIOs through gpiolib, which can
  be disabled on some platforms.
* The clocksource code cannot be built on platforms that don't
  use modern timekeeping but rely on gettimeoffset.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The Freescale FlexTimer Module time reference is a 16-bit counter
that can be used as an unsigned or signed increase counter.

CNTIN defines the starting value of the count and MOD defines the
final value of the count. The value of CNTIN is loaded into the FTM
counter, and the counter increments until the value of MOD is reached,
at which point the counter is reloaded with the value of CNTIN. That's
also when an overflow interrupt will be generated.

Here using the 'evt' prefix or postfix as clock event device and
the 'src' as clock source device.
Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.

[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.

[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.

[dlezcano] : refreshed against latest modifications: kmalloc -> kzalloc
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>

The site-specific OOM messages are unnecessary, because they
duplicate the MM subsystem generic OOM message.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>